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* UefiCpuPkg/SmmCpuFeaturesLib: Clean up header file inclusion in SmmStm.cAbner Chang2022-11-021-3/+0
| | | | | | | | | | | | | | | | BZ# 4093: Abstract SmmCpuFeaturesLib for sharing common code Remove the header files those are already included in CpuFeatureLib.h. Signed-off-by: Abner Chang <abner.chang@amd.com> Cc: Abdul Lateef Attar <abdattar@amd.com> Cc: Garrett Kirkendall <garrett.kirkendall@amd.com> Cc: Paul Grimes <paul.grimes@amd.com> Cc: Eric Dong <eric.dong@intel.com> Cc: Ray Ni <ray.ni@intel.com> Cc: Rahul Kumar <rahul1.kumar@intel.com> Reviewed-by: Ray Ni <ray.ni@intel.com>
* UefiCpuPkg/SmmCpuFeaturesLib: Abstract arch dependent codeAbner Chang2022-11-026-205/+227
| | | | | | | | | | | | | | | | | | | | BZ# 4093: Abstract SmmCpuFeaturesLib for sharing common code This change stripped away the code that can be shared with other archs or vendors from Intel implementation and put in to the common file, leaves the Intel X86 implementation in the IntelSmmCpuFeatureLib. Also updates the header file and INF file. Signed-off-by: Abner Chang <abner.chang@amd.com> Cc: Abdul Lateef Attar <abdattar@amd.com> Cc: Garrett Kirkendall <garrett.kirkendall@amd.com> Cc: Paul Grimes <paul.grimes@amd.com> Cc: Eric Dong <eric.dong@intel.com> Cc: Ray Ni <ray.ni@intel.com> Cc: Rahul Kumar <rahul1.kumar@intel.com> Reviewed-by: Ray Ni <ray.ni@intel.com>
* UefiCpuPkg/SmmCpuFeaturesLib: Rename the common C fileAbner Chang2022-11-024-3/+3
| | | | | | | | | | | | | | | | | | | | BZ# 4093: Abstract SmmCpuFeaturesLib for sharing common code Rename SmmCpuFeaturesLiCommon.c to IntelSmmCpuFeaturesLib, because it was developed specifically for Intel implementation. The code that can be shared by other archs or vendors will be stripped away and put in the common file in the next patch. Signed-off-by: Abner Chang <abner.chang@amd.com> Cc: Abdul Lateef Attar <abdattar@amd.com> Cc: Garrett Kirkendall <garrett.kirkendall@amd.com> Cc: Paul Grimes <paul.grimes@amd.com> Cc: Eric Dong <eric.dong@intel.com> Cc: Ray Ni <ray.ni@intel.com> Cc: Rahul Kumar <rahul1.kumar@intel.com> Reviewed-by: Ray Ni <ray.ni@intel.com>
* UefiCpuPkg: Restore HpetTimer after CpuExceptionHandlerLib testTan, Dun2022-10-282-1/+30
| | | | | | | | | | | | | | | | | | | | | | Disable/Restore HpetTimer before and after running the Dxe CpuExceptionHandlerLib unit test module. During the UnitTest, a new Idt is initialized for the test. There is no handler for timer intrrupt in this new idt. After the test module, HpetTimer does not work any more since the comparator value register and main counter value register for timer does not match. To fix this issue, disable/restore HpetTimer before and after Unit Test if HpetTimer driver has been dispatched. We don't need to send Apic Eoi in this unit test module.When disabling timer, after RaiseTPL(), if there is a pending timer interrupt, bit64 of Interrupt Request Register (IRR) will be set to 1 to indicate there is a pending timer interrupt. After RestoreTPL(), CPU will handle the pending interrupt in IRR.Then TimerInterruptHandler calls SendApicEoi(). Signed-off-by: Dun Tan <dun.tan@intel.com> Cc: Eric Dong <eric.dong@intel.com> Reviewed-by: Ray Ni <ray.ni@intel.com> Cc: Rahul Kumar <rahul1.kumar@intel.com> Cc: Michael D Kinney <michael.d.kinney@intel.com>
* UefiCpuPkg/Test: Add unit tests for MP service PPI and ProtocolJason Lou2022-10-177-0/+3218
| | | | | | | | | | | | | The code changes add unit tests based on current UnitTestFramework. EdkiiPeiMpServices2PpiPeiUnitTest PEI module is used to test EdkiiPeiMpServices2Ppi and EfiMpServiceProtocolDxeUnitTest DXE driver is used to test EfiMpServiceProtocol. Signed-off-by: Jason Lou <yun.lou@intel.com> Reviewed-by: Ray Ni <ray.ni@intel.com> Cc: Eric Dong <eric.dong@intel.com> Cc: Laszlo Ersek <lersek@redhat.com> Cc: Rahul Kumar <rahul1.kumar@intel.com>
* UefiCpuPkg: Add R8/R9 etc in EccCheck ExceptionListTan, Dun2022-10-171-1/+9
| | | | | | | | | | | | | Add GENERAL_REGISTER.R8/R9 etc in EccCheck ExceptionList of UefiCpuPkg/UefiCpuPkg.ci.yaml to pass CI EccCheck.R8/R9 in structure GENERAL_REGISTER of CpuExceptionHandlerTest.h lead to EccCheck failure since no lower case characters in R8/R9/R10 etc. Signed-off-by: Dun Tan <dun.tan@intel.com> Cc: Eric Dong <eric.dong@intel.com> Reviewed-by: Ray Ni <ray.ni@intel.com> Cc: Rahul Kumar <rahul1.kumar@intel.com>
* UefiCpuPkg: Add Pei/DxeCpuExceptionHandlerLibUnitTest in dscTan, Dun2022-10-171-0/+7
| | | | | | | | | Add Pei/DxeCpuExceptionHandlerLibUnitTest module in UefiCpuPkg.dsc Signed-off-by: Dun Tan <dun.tan@intel.com> Cc: Eric Dong <eric.dong@intel.com> Reviewed-by: Ray Ni <ray.ni@intel.com> Cc: Rahul Kumar <rahul1.kumar@intel.com>
* UefiCpuPkg: Add Unit tests for PeiCpuExceptionHandlerLibTan, Dun2022-10-175-0/+617
| | | | | | | | | | | | The previous change adds unit test for DxeCpuExeptionHandlerLib in 64bit mode. This change create a PEIM to add unit test for PeiCpuExceptionHandlerLib based on previous change.It can run in both 32bit and 64bit modes. Signed-off-by: Dun Tan <dun.tan@intel.com> Cc: Eric Dong <eric.dong@intel.com> Reviewed-by: Ray Ni <ray.ni@intel.com> Cc: Rahul Kumar <rahul1.kumar@intel.com>
* UefiCpuPkg: Add Unit tests for DxeCpuExceptionHandlerLibTan, Dun2022-10-176-0/+1864
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Add target based unit tests for the DxeCpuExceptionHandlerLib. A DXE driver is created to test DxeCpuExceptionHandlerLib. Four test cases are created in this Unit Test module: a.Test if exception handler can be registered/unregistered for no error code exception.In the test case, only no error code exception is triggered and tested by INTn instruction. b.Test if exception handler can be registered/unregistered for GP and PF. In the test case, GP exception is triggered and tested by setting CR4_RESERVED_BIT to 1. PF exception is triggered by writting to not-present or RO address. c.Test if CpuContext is consistent before and after exception. In this test case: 1.Set Cpu register to mExpectedContextInHandler before exception. 2.Trigger exception specified by ExceptionType. 3.Store SystemContext in mActualContextInHandler and set SystemContext to mExpectedContextAfterException in handler. 4.After return from exception, store Cpu registers in mActualContextAfterException. The expectation is: 1.Register values in mActualContextInHandler are the same with register values in mExpectedContextInHandler. 2.Register values in mActualContextAfterException are the same with register values mActualContextAfterException. d.Test if stack overflow can be captured by CpuStackGuard in both Bsp and AP. In this test case, stack overflow is triggered by a funtion which calls itself continuously. This test case triggers stack overflow in both BSP and AP. All AP use same Idt with Bsp. The expectation is: 1. PF exception is triggered (leading to a DF if sepereated stack is not prepared for PF) when Rsp<=StackBase+SIZE_4KB since [StackBase, StackBase + SIZE_4KB] is marked as not present in page table when PcdCpuStackGuard is TRUE. 2. Stack for PF/DF exception handler in both Bsp and AP is succussfully switched by InitializeSeparateExceptionStacks. Signed-off-by: Dun Tan <dun.tan@intel.com> Cc: Eric Dong <eric.dong@intel.com> Reviewed-by: Ray Ni <ray.ni@intel.com> Cc: Rahul Kumar <rahul1.kumar@intel.com>
* UefiCpuPkg/CpuPageTableLib:Support PAE paging for PageTableParseTan, Dun2022-10-171-2/+1
| | | | | | | | | Support PAE paging for PageTableParse API in CpuPageTableLib. Signed-off-by: Dun Tan <dun.tan@intel.com> Cc: Eric Dong <eric.dong@intel.com> Reviewed-by: Ray Ni <ray.ni@intel.com> Cc: Rahul Kumar <rahul1.kumar@intel.com>
* UefiCpuPkg:Add RegisterExceptionHandler in PeiCpuExceptionHandlerLibLiu, Zhiguang2022-10-171-1/+37
| | | | | | | | | | The PEI instance of the CpuExceptionHandlerLib didn't implement the RegisterCpuInterruptHandler() API. This patch adds the missing API. Signed-off-by: Zhiguang Liu <zhiguang.liu@intel.com> Cc: Eric Dong <eric.dong@intel.com> Reviewed-by: Ray Ni <ray.ni@intel.com> Cc: Rahul Kumar <rahul1.kumar@intel.com>
* UefiCpuPkg: Reset a parameter when BSP Exit in CPU relaxed mode.Zhihao Li2022-10-081-2/+3
| | | | | | | | | | | | | | REF: https://bugzilla.tianocore.org/show_bug.cgi?id=4083 In CPU relaxed mode, it doesn't reset the value of mSmmMpSyncData->AllApArrivedWithException when BSP exit smm mode. So this patch will reset this variable. Cc: Eric Dong <eric.dong@intel.com> Reviewed-by: Ray Ni <ray.ni@intel.com> Signed-off-by: Zhihao Li <zhihao.li@intel.com> Reviewed-by: Abner Chang <abner.chang@amd.com>
* UefiCpuPkg/CpuExceptionHandlerLib: Code optimization to allow bigger stackTan, Dun2022-10-082-2/+8
| | | | | | | | | | | | This commit is a code optimization to allow bigger seperate stack size in ArchSetupExceptionStack. In previous code logic, CPU_STACK_ALIGNMENT bytes will be wasted if StackTop is already CPU_STACK_ALIGNMENT aligned. Signed-off-by: Dun Tan <dun.tan@intel.com> Cc: Eric Dong <eric.dong@intel.com> Reviewed-by: Ray Ni <ray.ni@intel.com> Cc: Rahul Kumar <rahul1.kumar@intel.com> Reviewed-by: Abner Chang <abner.chang@amd.com>
* UefiCpuPkg: Enhance logic in InitializeMpExceptionStackSwitchHandlersLiu, Zhiguang2022-08-312-80/+132
| | | | | | | | | | Parallelly run the function to SeparateExceptionStacks for all CPUs and allocate buffers together for better performance. Cc: Eric Dong <eric.dong@intel.com> Reviewed-by: Ray Ni <ray.ni@intel.com> Cc: Rahul Kumar <rahul1.kumar@intel.com> Signed-off-by: Zhiguang Liu <zhiguang.liu@intel.com>
* UefiCpuPkg: Use Top of each AP's stack to save CpuMpDataYuanhao Xie2022-08-315-13/+59
| | | | | | | | | | | | To remove the dependency of CPU register, 4/8 byte at the top of the stack is occupied for CpuMpData. BIST information is also taken care here. This modification is only for PEI phase, since in DXE phase CpuMpData is accessed via global variable. Signed-off-by: Yuanhao Xie <yuanhao.xie@intel.com> Cc: Eric Dong <eric.dong@intel.com> Reviewed-by: Ray Ni <ray.ni@intel.com> Cc: Rahul Kumar <rahul1.kumar@intel.com>
* UefiCpuPkg: Simplify the implementation when separate exception stacksLiu, Zhiguang2022-08-318-383/+173
| | | | | | | | | | | The API of InitializeSeparateExceptionStacks is just changed before, and makes the struct CPU_EXCEPTION_INIT_DATA an internal definition. Furthermore, we can even remove the struct to make core simpler. Cc: Eric Dong <eric.dong@intel.com> Reviewed-by: Ray Ni <ray.ni@intel.com> Cc: Rahul Kumar <rahul1.kumar@intel.com> Signed-off-by: Zhiguang Liu <zhiguang.liu@intel.com>
* UefiCpuPkg/MpInitLib: Simplify logic in SwitchBspLiu, Zhiguang2022-08-314-63/+56
| | | | | | | | | | | | | When switch bsp, old bsp and new bsp put CR0/CR4 into stack, and put IDT and GDT register into a structure. After they exchange their stack, they restore these registers. This logic is now implemented by assembly code. This patch aims to reuse (Save/Restore)VolatileRegisters function to replace such assembly code for better code readability. Cc: Eric Dong <eric.dong@intel.com> Reviewed-by: Ray Ni <ray.ni@intel.com> Cc: Rahul Kumar <rahul1.kumar@intel.com> Signed-off-by: Zhiguang Liu <zhiguang.liu@intel.com>
* UefiCpuPkg: Add PCD to control SMRR enable & SmmFeatureControl supportWu, Jiaxin2022-08-316-23/+48
| | | | | | | | | | | | | | | REF: https://bugzilla.tianocore.org/show_bug.cgi?id=3962 Two SMM variables (mSmrrSupported & mSmmFeatureControlSupported) are global variables, they control whether the SMRR and SMM Feature Control MSR will be restored respectively. To avoid the TOCTOU, add PCD to control SMRR & SmmFeatureControl enable. Cc: Eric Dong <eric.dong@intel.com> Reviewed-by: Ray Ni <ray.ni@intel.com> Cc: Star Zeng <star.zeng@intel.com> Cc: Michael D Kinney <michael.d.kinney@intel.com> Signed-off-by: Jiaxin Wu <jiaxin.wu@intel.com>
* UefiCpuPkg/MpInitLib: Fix potential issue when IDT table is at above 4GLiu, Zhiguang2022-08-311-3/+5
| | | | | | | | | | | | | | | | | Currently, when waking up AP, IDT table of AP will be set in 16 bit code, and assume the IDT table base is 32 bit. However, the IDT table is created by BSP. Issue will happen if the BSP allocates memory above 4G for BSP's IDT table. Moreover, even the IDT table location is below 4G, the handler function inside the IDT table is 64 bit, and it won't take effect until CPU transfers to 64 bit long mode. There is no benefit to set IDT table in such an early phase. To avoid such issue, this patch moves the LIDT instruction into 64 bit code. Cc: Eric Dong <eric.dong@intel.com> Reviewed-by: Ray Ni <ray.ni@intel.com> Cc: Rahul Kumar <rahul1.kumar@intel.com> Signed-off-by: Zhiguang Liu <zhiguang.liu@intel.com>
* UefiCpuPkg/CpuPageTableLib/UnitTest: Add host based unit testZhiguang Liu2022-08-319-1/+7266
| | | | | | | | | | | | | | | | | | | | | | Add host based unit tests for the CpuPageTableLib services. Unit test focuses on PageTableMap function, containing two kinds of test cases: manual test case and random test case. Manual test case creates some corner case to test function PageTableMap. Random test case generates multiple random memory entries (with random attribute) as the input of function PageTableMap to get the output pagetable. Output pagetable will be validated and be parsed to get output memory entries, and then the input and output memory entries will be compared to verify the functionality. The unit test is not perfect yet. There are options for random test, and some of them control the test coverage, and some option are not ready. Will enhance in the future. Cc: Eric Dong <eric.dong@intel.com> Reviewed-by: Ray Ni <ray.ni@intel.com> Cc: Rahul Kumar <rahul1.kumar@intel.com> Signed-off-by: Zhiguang Liu <zhiguang.liu@intel.com>
* Revert "UefiCpuPkg/CpuPageTableLib/UnitTest: Add host based unit test"Liming Gao2022-08-289-7266/+1
| | | | | | | | | This reverts commit 2812668bfc121ee792cf3302195176ef4a2ad0bc for tag202208. This feature will be merged after stable tag 202208 is created. Signed-off-by: Liming Gao <gaoliming@byosoft.com.cn> Reviewed-by: Zhiguang Liu <zhiguang.liu@intel.com> Acked-by: Ard Biesheuvel <ardb@kernel.org>
* UefiCpuPkg/CpuPageTableLib/UnitTest: Add host based unit testZhiguang Liu2022-08-169-1/+7266
| | | | | | | | | | | | | | | | | | | | | | Add host based unit tests for the CpuPageTableLib services. Unit test focuses on PageTableMap function, containing two kinds of test cases: manual test case and random test case. Manual test case creates some corner case to test function PageTableMap. Random test case generates multiple random memory entries (with random attribute) as the input of function PageTableMap to get the output pagetable. Output pagetable will be validated and be parsed to get output memory entries, and then the input and output memory entries will be compared to verify the functionality. The unit test is not perfect yet. There are options for random test, and some of them control the test coverage, and some option are not ready. Will enhance in the future. Cc: Eric Dong <eric.dong@intel.com> Reviewed-by: Ray Ni <ray.ni@intel.com> Cc: Rahul Kumar <rahul1.kumar@intel.com> Signed-off-by: Zhiguang Liu <zhiguang.liu@intel.com>
* UefiCpuPkg/PiSmmCpuDxeSmm: Remove mInternalCr3 in PiSmmCpuDxeSmmDun Tan2022-08-154-147/+96
| | | | | | | | | | | | | | This patch is code refactoring and doesn't change any functionality. Remove mInternalCr3 in PiSmmCpuDxe pagetable related code. In previous code, mInternalCr3 is used to pass address of page table which is different from Cr3 register in different level of SetMemoryAttributes function. Now remove it and pass the page table base address from the root function parameter to simplify the code logic. Signed-off-by: Dun Tan <dun.tan@intel.com> Cc: Eric Dong <eric.dong@intel.com> Cc: Rahul Kumar <rahul1.kumar@intel.com> Reviewed-by: Ray Ni <ray.ni@intel.com>
* UefiCpuPkg/PiSmmCpuDxeSmm: Add a new mIsShadowStack flagDun Tan2022-08-151-4/+6
| | | | | | | | | | | | | This patch is code refactoring and doesn't change any functionality. Add a new mIsShadowStack flag to identify whether current memory is shadow stack. Previous smm code logic regards a RO range as shadow stack and set the dirty bit in corresponding page table entry if mInternalCr3 is not 0, which may be confusing. Signed-off-by: Dun Tan <dun.tan@intel.com> Cc: Eric Dong <eric.dong@intel.com> Cc: Rahul Kumar <rahul1.kumar@intel.com> Reviewed-by: Ray Ni <ray.ni@intel.com>
* CpuPageTableLib: define IA32_PAGE_LEVEL enum type internallyRay Ni2022-08-092-6/+14
| | | | | | | | The change doesn't change functionality behavior. Signed-off-by: Ray Ni <ray.ni@intel.com> Cc: Zhiguang Liu <zhiguang.liu@intel.com> Reviewed-by: Eric Dong <eric.dong@intel.com>
* CpuPageTableLib: Fix bug that wrongly requires extra size for mappingRay Ni2022-08-091-8/+5
| | | | | | | | | | | | | | | | | | | | | | With following paging structure to map [2M-4K, 2M] as P = 1, RW = 0, [2M, 4M] as P = 1, RW = 1: PML4[0] -> PDPTE[0] -> PDE[0](RW = 0) -> PTE[255](P = 0, RW = 0) -> PDE[1](RW = 1) When a new request to map [2M-4K, 2M+4K] as P = 1, RW = 1, CpuPageTableMap() wrongly requests 4K buffer size for the new mapping request. But in fact, for [2M-4K, 2M] request, PTE[255] can be changed in place, for [2M, 2M+4K], no change is needed because PDE[1].RW = 1 already. The change fixes the bug. Signed-off-by: Ray Ni <ray.ni@intel.com> Signed-off-by: Zhiguang Liu <zhiguang.liu@intel.com> Reviewed-by: Eric Dong <eric.dong@intel.com>
* CpuPageTableLib: Fix a bug to avoid unnecessary changing to page tableRay Ni2022-08-091-9/+32
| | | | | | | | | | | | | | | | | | | | | | | | | With the following paging structure that maps [0, 2G] with ReadWrite bit set. PML4[0] --> PDPTE[0] --> PDE[0-255] \-> PDPTE[1] --> PDE[0-255] If ReadWrite bit is cleared in PML4[0] and PageTableMap() is called to change [0, 2M] as read-only, today's logic unnecessarily changes the paging structure in 2 aspects: 1. When setting PageTableBaseAddress in the entry, the code clears all attributes. 2. Even the ReadWrite bit in parent entry is not set, the code clears the ReadWrite bit in the leaf entry. First change is wrong. It should not change other attributes when setting the PA. Second change is unnecessary. Because the parent entry already declares the whole region as read-only, there is no need to clear ReadWrite bit in the leaf entry again. Signed-off-by: Zhiguang Liu <zhiguang.liu@intel.com> Signed-off-by: Ray Ni <ray.ni@intel.com> Reviewed-by: Eric Dong <eric.dong@intel.com>
* CpuPageTableLib: Fix parent attributes are not inherited properlyRay Ni2022-08-092-17/+147
| | | | | | | | | | | | | | | | | | | | | | | | | | | With the following paging structure that maps [0, 2G] with ReadWrite bit set. PML4[0] --> PDPTE[0] --> PDE[0-255] \-> PDPTE[1] --> PDE[0-255] If ReadWrite bit is cleared in PML4[0] and PageTableMap() is called to change [0, 2M] as writable, today's logic doesn't inherit the parent entry's attributes when determining the child entry's attributes. It just sets the PDPTE[0].PDE[0].ReadWrite bit. But since the PML4[0].ReadWrite is 0, [0, 2M] is still read-only. The change fixes the bug. If the inheritable attributes in ParentPagingEntry conflicts with the requested attributes, let the child entries take the parent attributes and loosen the attribute in the parent entry. E.g.: when PDPTE[0].ReadWrite = 0 but caller wants to map [0-2MB as ReadWrite = 1 (PDE[0].ReadWrite = 1), we need to change PDPTE[0].ReadWrite = 1 and let all PDE[0-255].ReadWrite = 0 first. Then change PDE[0].ReadWrite = 1. Signed-off-by: Zhiguang Liu <zhiguang.liu@intel.com> Signed-off-by: Ray Ni <ray.ni@intel.com> Reviewed-by: Eric Dong <eric.dong@intel.com>
* CpuPageTableLib: Avoid treating non-leaf entry as leaf oneRay Ni2022-08-091-4/+7
| | | | | | | | | | | | Today's logic wrongly treats the non-leaf entry as leaf entry and updates its paging attributes. The patch fixes the bug to only update paging attributes for non-present entries or leaf entries. Signed-off-by: Ray Ni <ray.ni@intel.com> Signed-off-by: Zhiguang Liu <zhiguang.liu@intel.com> Reviewed-by: Eric Dong <eric.dong@intel.com>
* CpuPageTableLib: Split the page entry when LA is aligned but PA is notRay Ni2022-08-091-1/+6
| | | | | | | | | | | | | When PageTableMap() is called to create non 1:1 mapping such as [0, 1G) to [8K, 1G+8K), it should split the page entry to the 4K page level, but old logic has a bug that it just uses 1G page entry. The patch fixes the bug. Signed-off-by: Zhiguang Liu <zhiguang.liu@intel.com> Reviewed-by: Ray Ni <ray.ni@intel.com> Reviewed-by: Eric Dong <eric.dong@intel.com>
* CpuPageTableLib: Refactor the logicRay Ni2022-08-091-1/+1
| | | | | | | | | | | | | | | | | | | | | | | | The patch replaces LinearAddress + Offset == RegionStart with ((LinearAddress + Offset) & RegionMask) == 0 The replace should not cause any behavior change. Because: 1. In first loop of while when LinearAddress + Offset == RegionStart, because the lower "BitStart" bits of RegionStart are all-zero, all lower "BitStart" bits of (LinearAddress + Offset) are all-zero. Because all lower "BitStart" bits of RegionMask is all-one and bits are all-zero, ((LinearAddress + Offset) & RegionMask) == 0. 2. In following loops of the while, even RegionStart is increased by RegionLength, the lower "BitStart" bits are still all-zero. So the two expressions still semantically equal to each other. Signed-off-by: Ray Ni <ray.ni@intel.com> Cc: Zhiguang Liu <zhiguang.liu@intel.com> Reviewed-by: Eric Dong <eric.dong@intel.com>
* CpuPageTableLib: Fix a bug when a bit is 1 in Attribute, 0 in MaskRay Ni2022-08-091-1/+1
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | To reproduce the issue: UINTN PageTable; VOID *Buffer; UINTN PageTableBufferSize; IA32_MAP_ATTRIBUTE Attribute; IA32_MAP_ATTRIBUTE Mask; RETURN_STATUS Status; Attribute.Uint64 = 0; Mask.Uint64 = 0; PageTableBufferSize = 0; PageTable = 0; Buffer = NULL; Attribute.Bits.Present = 1; Attribute.Bits.Nx = 1; Mask.Bits.Present = 1; Mask.Uint64 = MAX_UINT64; // // Create page table to cover [0, 10M) // Status = PageTableMap ( &PageTable, PagingMode, Buffer, &PageTableBufferSize, 0, (UINT64)SIZE_2MB * 5, &Attribute, &Mask ); ASSERT (Status == RETURN_BUFFER_TOO_SMALL); Buffer = AllocatePages (EFI_SIZE_TO_PAGES (PageTableBufferSize)); Status = PageTableMap ( &PageTable, PagingMode, Buffer, &PageTableBufferSize, 0, (UINT64)SIZE_2MB * 5, &Attribute, &Mask ); ASSERT (Status == RETURN_SUCCESS); // // Change the mapping for [0, 4KB) // No change actually. Just clear Nx bit in Mask. // Mask.Bits.Nx = 0; PageTableBufferSize = 0; Status = PageTableMap ( &PageTable, PagingMode, NULL, &PageTableBufferSize, 0, (UINT64)SIZE_4KB, &Attribute, &Mask ); ASSERT (Status == RETURN_SUCCESS); // FAIL!! The root cause is when comparing the existing mapping attributes against the requested one, Mask is not used but it should be used. Signed-off-by: Zhiguang Liu <zhiguang.liu@intel.com> Reviewed-by: Ray Ni <ray.ni@intel.com> Reviewed-by: Eric Dong <eric.dong@intel.com>
* UefiCpuPkg/CpuPageTableLib: Return error on invalid parametersRay Ni2022-08-091-0/+7
| | | | | | | | | When LinearAddress or Length is not aligned on 4KB, PageTableMap() should return Invalid Parameter. Signed-off-by: Zhiguang Liu <zhiguang.liu@intel.com> Reviewed-by: Ray Ni <ray.ni@intel.com> Reviewed-by: Eric Dong <eric.dong@intel.com>
* UefiCpuPkg: Create CpuPageTableLib for manipulating X86 paging structsRay Ni2022-08-097-1/+1247
| | | | | | | | | | | | | | | | | | The lib includes two APIs: * PageTableMap It creates/updates mapping from LA to PA. The implementation only supports paging structures used in 64bit mode now. PAE paging structure support will be added in future. * PageTableParse It parses the page table and returns the mapping relations in an array of IA32_MAP_ENTRY. It passed some stress tests. These test code will be upstreamed in other patches following edk2 Unit Test framework. Signed-off-by: Ray Ni <ray.ni@intel.com> Reviewed-by: Eric Dong <eric.dong@intel.com>
* UefiCpuPkg: Simplify the struct definition of CPU_EXCEPTION_INIT_DATALiu, Zhiguang2022-08-095-161/+145
| | | | | | | | | | | | CPU_EXCEPTION_INIT_DATA is now an internal implementation of CpuExceptionHandlerLib. Union can be removed since Ia32 and X64 have the same definition. Also, two fields (Revision and InitDefaultHandlers)are useless, can be removed. Cc: Eric Dong <eric.dong@intel.com> Reviewed-by: Ray Ni <ray.ni@intel.com> Cc: Rahul Kumar <rahul1.kumar@intel.com> Signed-off-by: Zhiguang Liu <zhiguang.liu@intel.com>
* MdeModulePkg: Move CPU_EXCEPTION_INIT_DATA to UefiCpuPkgLiu, Zhiguang2022-08-091-1/+68
| | | | | | | | | | | | | | | Since the API InitializeSeparateExceptionStacks is simplified and does't use the struct CPU_EXCEPTION_INIT_DATA, CPU_EXCEPTION_INIT_DATA become a inner implementation of CpuExcetionHandlerLib. Cc: Eric Dong <eric.dong@intel.com> Reviewed-by: Ray Ni <ray.ni@intel.com> Cc: Rahul Kumar <rahul1.kumar@intel.com> Cc: Leif Lindholm <quic_llindhol@quicinc.com> Cc: Dandan Bi <dandan.bi@intel.com> Cc: Liming Gao <gaoliming@byosoft.com.cn> Cc: Jian J Wang <jian.j.wang@intel.com> Signed-off-by: Zhiguang Liu <zhiguang.liu@intel.com>
* UefiCpuPkg: Simplify InitializeSeparateExceptionStacksLiu, Zhiguang2022-08-097-320/+260
| | | | | | | | | | | | | | | | Hide the Exception implementation details in CpuExcetionHandlerLib and caller only need to provide buffer Cc: Eric Dong <eric.dong@intel.com> Reviewed-by: Ray Ni <ray.ni@intel.com> Cc: Rahul Kumar <rahul1.kumar@intel.com> Cc: Leif Lindholm <quic_llindhol@quicinc.com> Cc: Dandan Bi <dandan.bi@intel.com> Cc: Liming Gao <gaoliming@byosoft.com.cn> Cc: Jian J Wang <jian.j.wang@intel.com> Cc: Ard Biesheuvel <ardb+tianocore@kernel.org> Reviewed-by: Sami Mujawar <sami.mujawar@arm.com> Signed-off-by: Zhiguang Liu <zhiguang.liu@intel.com>
* UefiCpuPkg: Fix nasm warning "signed byte value exceeds"Zhiguang Liu2022-07-253-11/+9
| | | | | | | | | | | | | | | | | | | | | Currently, "push byte %[Vector]" causes nasm warning when Vector is larger than 0x7F. This is because push accepts a signed value, and byte means signed int8. Maximum signed int8 is 0x7F. When Vector is larger the 0x7F, for example, when Vector is 255, byte 255 turns to -1, and causes the warning "signed byte value exceeds". To avoid such warning, use dword instead of byte, this will increase 3 bytes for each IdtVector. For IA32, the size of IdtVector will increase from 10 bytes to 13 bytes. For X64, the size of IdtVector will increase from 15 bytes to 18 bytes. Cc: Eric Dong <eric.dong@intel.com> Cc: Ray Ni <ray.ni@intel.com> Cc: Rahul Kumar <rahul1.kumar@intel.com> Cc: Debkumar De <debkumar.de@intel.com> Cc: Harry Han <harry.han@intel.com> Cc: Catharine West <catharine.west@intel.com> Reviewed-by: Ray Ni <ray.ni@intel.com> Signed-off-by: Zhiguang Liu <zhiguang.liu@intel.com>
* UefiCpuPkg: Update SEC_IDT_TABLE structKuo, Ted2022-07-142-2/+3
| | | | | | | | | | | | | | | | | REF:https://bugzilla.tianocore.org/show_bug.cgi?id=3957 The reserved IDT table size in SecCore is too small for X64. Changed the type of IdtTable in SEC_IDT_TABLE from UINT64 to IA32_IDT_GATE_DESCRIPTOR to have sufficient size reserved in IdtTable for X64. dff Cc: Chasel Chiu <chasel.chiu@intel.com> Cc: Nate DeSimone <nathaniel.l.desimone@intel.com> Cc: Ray Ni <ray.ni@intel.com> Cc: Ashraf Ali S <ashraf.ali.s@intel.com> Cc: Debkumar De <debkumar.de@intel.com> Cc: Harry Han <harry.han@intel.com> Cc: Catharine West <catharine.west@intel.com> Signed-off-by: Ted Kuo <ted.kuo@intel.com> Reviewed-by: Ray Ni <ray.ni@intel.com>
* UefiCpuPkg/SecCore: Add debug messages to illuminate data flowOram, Isaac W2022-07-081-0/+37
| | | | | | | | | | | | | Add debug messages to make it easier to verify PlatformSecLib is passing the data properly. Reviewed-by: Eric Dong <eric.dong@intel.com> Cc: Ray Ni <ray.ni@intel.com> Cc: Rahul Kumar <rahul1.kumar@intel.com> Cc: Debkumar De <debkumar.de@intel.com> Cc: Harry Han <harry.han@intel.com> Cc: Catharine West <catharine.west@intel.com> Signed-off-by: Isaac Oram <isaac.w.oram@intel.com>
* UefiCpuPkg: CpuDxe: Set RW and P Attributes on Split PagesRay Ni2022-06-231-3/+5
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | A memory range can be submitted for attribute changes which is large enough to not require a page split during the attribute update. Consider the following scenario: 1. An attribute update removed the RW attribute on a range large enough to not require a page split. 2. Later, an attributes update is called to re-add the RW attribute for a subsection of that larger page which requires a split 3. The attribute update logic performs a page split, so now the parent and child pages have matching attributes 4. Then, the attribute update logic changes the child page to have the RW attribute. 5. The child page would then correctly have the RW attribute added but the parent page would still have the RW attribute removed which will cause an improper access violation. The page being split should have loose attributes to accommodate the above case. The split page should always have the attributes set so the lowest level page frame determines the access rights as detailed in 4.10.2.2 of the Intel 64 and IA-32 Architectures Software Developer Manual. Setting the User/Supervisor attribute shouldn't be necessary. Cc: Eric Dong <eric.dong@intel.com> Reviewed-by: Ray Ni <ray.ni@intel.com> Cc: Rahul Kumar <rahul1.kumar@intel.com> Signed-off-by: Taylor Beebe <t@taylorbeebe.com>
* MpInitLib: Move the Above1Mb vector allocation to MpInitLibInitializeRay Ni2022-06-101-24/+29
| | | | | | | | | | | | | | | | | The AP vector consists of 2 parts: 1. the initial 16-bit code that should be under 1MB and page aligned. 2. the 32-bit/64-bit code that can be anywhere in the memory with any alignment. The need of part #2 is because the memory under 1MB is temporary "stolen" for use and will "give" back after all AP wake up. The range of memory is not marked as code page in page table. CPU may trigger exception as soon as NX is enabled. The part #2 memory allocation can be done in the MpInitLibInitialize. Signed-off-by: Ray Ni <ray.ni@intel.com> Reviewed-by: Eric Dong <eric.dong@intel.com>
* MpInitLib: Only allocate below 1MB memory for 16bit codeRay Ni2022-06-103-56/+46
| | | | | | | | | | | | | | | | | | | Today's implementation allocates below 1MB memory for the 16bit, 32bit and 64bit code. But it's not necessary since now the 32bit and 64bit code run at high memory no matter in PEI and DXE phase. The patch simplifies the logic to remove the code that handles the case when WakeupBufferHigh is 0. It also reduce the memory foot print under 1MB by allocating memory for 16bit code only. MP_CPU_EXCHANGE_INFO is still under 1MB which is immediate after the 16bit code. Signed-off-by: Ray Ni <ray.ni@intel.com> Reviewed-by: Eric Dong <eric.dong@intel.com>
* MpInitLib: Put SEV logic in separate fileRay Ni2022-06-106-172/+161
| | | | | | | | | | | | | | | | | | | | | | | | | | | The patch does several simplifications: 1. Treat SwitchToRealProc as part of RendezvousFunnelProc. So the common logic in MpLib.c doesn't need to be aware of SwitchToRealProc. As a result, SwitchToRealSize/Offset are removed from MP_ASSEMBLY_ADDRESS_MAP. 2. Move SwitchToRealProc to AmdSev.nasm. All other assembly code in AmdSev.nasm is called through OneTimeCall. Signed-off-by: Ray Ni <ray.ni@intel.com> Reviewed-by: Eric Dong <eric.dong@intel.com> Reviewed-by: Tom Lendacky <thomas.lendacky@amd.com> Tested-by: Tom Lendacky <thomas.lendacky@amd.com> Cc: Rahul Kumar <rahul1.kumar@intel.com> Cc: Michael Roth <michael.roth@amd.com> Cc: James Bottomley <jejb@linux.ibm.com> Cc: Min Xu <min.m.xu@intel.com> Cc: Jiewen Yao <jiewen.yao@intel.com> Cc: Jordan Justen <jordan.l.justen@intel.com> Cc: Ard Biesheuvel <ardb+tianocore@kernel.org> Cc: Erdem Aktas <erdemaktas@google.com> Cc: Gerd Hoffmann <kraxel@redhat.com>
* MpInitLib: remove unneeded global ASM_PFXRay Ni2022-06-102-15/+3
| | | | | | | | | global in NASM file is used for symbols that are referenced in C files. Remove unneeded global keyword in NASM file. Signed-off-by: Ray Ni <ray.ni@intel.com> Reviewed-by: Eric Dong <eric.dong@intel.com>
* MpInitLib: Allocate code buffer for PEI phaseRay Ni2022-06-104-8/+13
| | | | | | | | | | Today's implementation assumes PEI phase runs at 32bit so the execution-disable feature is not applicable. It's not always TRUE. The patch allocates 32bit&64bit code buffer for PEI phase as well. Signed-off-by: Ray Ni <ray.ni@intel.com> Reviewed-by: Eric Dong <eric.dong@intel.com>
* CpuException: Add InitializeSeparateExceptionStacksRay Ni2022-06-106-146/+60
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Today InitializeCpuExceptionHandlersEx is called from three modules: 1. DxeCore (links to DxeCpuExceptionHandlerLib) DxeCore expects it initializes the IDT entries as well as assigning separate stacks for #DF and #PF. 2. CpuMpPei (links to PeiCpuExceptionHandlerLib) and CpuDxe (links to DxeCpuExceptionHandlerLib) It's called for each thread for only assigning separate stacks for #DF and #PF. The IDT entries initialization is skipped because caller sets InitData->X64.InitDefaultHandlers to FALSE. Additionally, SecPeiCpuExceptionHandlerLib, SmmCpuExceptionHandlerLib also implement such API and the behavior of the API is simply to initialize IDT entries only. Because it mixes the IDT entries initialization and separate stacks assignment for certain exception handlers together, in order to know whether the function call only initializes IDT entries, or assigns stacks, we need to check: 1. value of InitData->X64.InitDefaultHandlers 2. library instance This patch cleans up the code to separate the stack assignment to a new API: InitializeSeparateExceptionStacks(). Only when caller calls the new API, the separate stacks are assigned. With this change, the SecPei and Smm instance can return unsupported which gives caller a very clear status. The old API InitializeCpuExceptionHandlersEx() is removed in this patch. Because no platform module is consuming the old API, the impact is none. Signed-off-by: Ray Ni <ray.ni@intel.com> Cc: Eric Dong <eric.dong@intel.com> Cc: Jian J Wang <jian.j.wang@intel.com>
* CpuException: Remove InitializeCpuInterruptHandlersRay Ni2022-06-106-209/+50
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | InitializeCpuExceptionHandlers() expects caller allocates IDT while InitializeCpuInterruptHandlers() allocates 256 IDT entries itself. InitializeCpuExceptionHandlers() fills max 32 IDT entries allocated by caller. If caller allocates 10 entries, the API just fills 10 IDT entries. The inconsistency between the two APIs makes code hard to unerstand and hard to share. Because there is only one caller (CpuDxe) for InitializeCpuInterruptHandler(), this patch updates CpuDxe driver to allocates 256 IDT entries then call InitializeCpuExceptionHandlers(). This is also a backward compatible change. With this change, InitializeCpuInterruptHandlers() is removed completely. And InitializeCpuExceptionHandlers() fills max 32 entries for PEI and SMM instance, max 256 entries for DXE instance. Such behavior matches to the original one. Signed-off-by: Ray Ni <ray.ni@intel.com> Cc: Eric Dong <eric.dong@intel.com>
* CpuException: Avoid allocating page but using global variablesRay Ni2022-06-101-19/+5
| | | | | Signed-off-by: Ray Ni <ray.ni@intel.com> Cc: Eric Dong <eric.dong@intel.com>
* CpuException: Init global variables in-placeRay Ni2022-06-102-13/+12
| | | | | | | | | Additionally removed two useless global variables: "SPIN_LOCK mDisplayMessageSpinLock" from SMM instance. "UINTN mEnabledInterruptNum" from DXE instance. Signed-off-by: Ray Ni <ray.ni@intel.com> Cc: Eric Dong <eric.dong@intel.com>
generated by cgit v1.2.3 (git 2.25.1) at 2024-07-02 22:58:46 +0000