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* UefiCpuPkg/PiSmmCpuDxeSmm: SMM_CPU_DATA_BLOCK is not clearedJeff Fan2016-07-201-1/+5
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | The commit 8b9311 changed the zeroing of mSmmMpSyncData of type SMM_DISPATCHER_MP_SYNC_DATA by the following patch. - ZeroMem (mSmmMpSyncData, mSmmMpSyncDataSize); + mSmmMpSyncData->SwitchBsp = FALSE; mSmmMpSyncDataSize not only includes SMM_DISPATCHER_MP_SYNC_DATA, but also includes the SMM_CPU_DATA_BLOCK array and one BOOLEAN variable array as shown here: mSmmMpSyncDataSize = sizeof (SMM_DISPATCHER_MP_SYNC_DATA) + (sizeof (SMM_CPU_DATA_BLOCK) + sizeof (BOOLEAN)) * gSmmCpuPrivate->SmmCoreEntryContext.NumberOfCpus; This patch restores the original ZeroMem() to clear all CPU Sync data. The commit 8b9311 may cause unexpected behavior. v2: Mentioned CandidateBsp array in comments to make it more accurate. Cc: Laszlo Ersek <lersek@redhat.com> Cc: Feng Tian <feng.tian@intel.com> Cc: Michael Kinney <michael.d.kinney@intel.com> Contributed-under: TianoCore Contribution Agreement 1.0 Signed-off-by: Jeff Fan <jeff.fan@intel.com> Reviewed-by: Feng Tian <feng.tian@intel.com> Reviewed-by: Laszlo Ersek <lersek@redhat.com> Reviewed-by: Michael Kinney <michael.d.kinney@intel.com>
* UefiCpuPkg/CpuDxe: StartupAllAPs in parallel modeJeff Fan2016-07-201-2/+2
| | | | | | | | | | | | | | SetMemoryAttributes() will sync BSP's MTRRs settings to all APs by StartupAllAPs service in serial mode. It may caused much performance impact if there are too much processors in system. This update is to invoke StartupAllAps in parallel mode. IA32 SDM does suggest to program MTRRs in parallel mode. Cc: Michael Kinney <michael.d.kinney@intel.com> Cc: Feng Tian <feng.tian@intel.com> Cc: Laszlo Ersek <lersek@redhat.com> Contributed-under: TianoCore Contribution Agreement 1.0 Signed-off-by: Jeff Fan <jeff.fan@intel.com> Reviewed-by: Feng Tian <feng.tian@intel.com>
* UefiCpuPkg/MtrrLib: Add notes for usage by BSP/APsJeff Fan2016-07-201-0/+4
| | | | | | | | | | | | Except for MtrrSetAllMtrrs(), others services are not suggested to be invoked by APs because they are not necessary and may invoke DEBUG() to dump MTRR setting. Cc: Feng Tian <feng.tian@intel.com> Cc: Michael Kinney <michael.d.kinney@intel.com> Cc: Laszlo Ersek <lersek@redhat.com> Contributed-under: TianoCore Contribution Agreement 1.0 Signed-off-by: Jeff Fan <jeff.fan@intel.com> Reviewed: Laszlo Ersek <lersek@redhat.com>
* UefiCpuPkg/MtrrLib: Remove MTRRs display from MtrrSetAllMtrrs()Jeff Fan2016-07-201-2/+0
| | | | | | | | | | | | | | | | MtrrSetAllMtrrs() maybe used by APs to sync BSP's MTRR settings. BSP's MTRR setting should be displayed if EFI_D_CACHE flag is set when MTRR updated. In MtrrSetAllMtrrs(), it's not necessary to display MTRR setting again due to the MTRR settings should be always same among BSP/APs. This updating could avoid APs output MTRR setting at the same time and make display message corrupted. Cc: Feng Tian <feng.tian@intel.com> Cc: Michael Kinney <michael.d.kinney@intel.com> Cc: Laszlo Ersek <lersek@redhat.com> Contributed-under: TianoCore Contribution Agreement 1.0 Signed-off-by: Jeff Fan <jeff.fan@intel.com> Reviewed-by: Laszlo Ersek <lersek@redhat.com> Reviewed-by: Michael Kinney <michael.d.kinney@intel.com>
* UefiCpuPkg/PiSmmCpuDxeSmm: remove superfluous ENDs from NASM sourceLaszlo Ersek2016-07-182-3/+0
| | | | | | | | | | | | | | | | | | | | Commits 28ee5816465b1 and 246cd9085f806 added these ENDs as part of the manual conversion from *.asm files. However, the ENDs makes no sense for NASM. Although they don't break the build, NASM complains about them: label alone on a line without a colon might be in error (This NASM warning category dates back to NASM 0.95, commit 6768eb71d8deb.) Remove the ENDs. Cc: Jeff Fan <jeff.fan@intel.com> Cc: Liming Gao <liming.gao@intel.com> Cc: Michael Kinney <michael.d.kinney@intel.com> Contributed-under: TianoCore Contribution Agreement 1.0 Signed-off-by: Laszlo Ersek <lersek@redhat.com> Reviewed-by: Liming Gao <liming.gao@intel.com>
* UefiCpuPkg/PiSmmCpuDxeSmm: Clean up CheckFeatureSupported()Jeff Fan2016-07-143-60/+3
| | | | | | | | | | | | | Removed EFIAPI and parameter from CheckFeatureSupported() and removed CheckProcessorFeature() totally. Cc: Michael Kinney <michael.d.kinney@intel.com> Cc: Feng Tian <feng.tian@intel.com> Contributed-under: TianoCore Contribution Agreement 1.0 Signed-off-by: Jeff Fan <jeff.fan@intel.com> Reviewed-by: Feng Tian <feng.tian@intel.com> Reviewed-by: Michael Kinney <michael.d.kinney@intel.com> Regression-tested-by: Laszlo Ersek <lersek@redhat.com>
* UefiCpuPkg/PiSmmCpuDxeSmm: Check XD/BTS features in SMM relocationJeff Fan2016-07-142-7/+9
| | | | | | | | | | | | | | | | CheckProcessorFeature() invokes MpService->StartupAllAps() to detect XD/BTS features on normal boot path. It's not necessary and may cause performance impact, because INIT-SIPI-SIPI must be sent to APs if APs are in hlt-loop mode. XD/BTS feature detection is moved to SmmInitHandler() in SMM relocation during normal boot path. Cc: Michael Kinney <michael.d.kinney@intel.com> Cc: Feng Tian <feng.tian@intel.com> Contributed-under: TianoCore Contribution Agreement 1.0 Signed-off-by: Jeff Fan <jeff.fan@intel.com> Reviewed-by: Feng Tian <feng.tian@intel.com> Reviewed-by: Michael Kinney <michael.d.kinney@intel.com> Regression-tested-by: Laszlo Ersek <lersek@redhat.com>
* UefiCpuPkg/PiSmmCpuDxeSmm: Add SMM S3 boot flagJeff Fan2016-07-141-0/+7
| | | | | | | | | | | | It will be set to TRUE during S3 resume. Cc: Michael Kinney <michael.d.kinney@intel.com> Cc: Feng Tian <feng.tian@intel.com> Contributed-under: TianoCore Contribution Agreement 1.0 Signed-off-by: Jeff Fan <jeff.fan@intel.com> Reviewed-by: Feng Tian <feng.tian@intel.com> Reviewed-by: Michael Kinney <michael.d.kinney@intel.com> Regression-tested-by: Laszlo Ersek <lersek@redhat.com>
* UefiCpuPkg/PiSmmCpuDxeSmm: Add MemoryMapped in SetProcessorRegister()Jeff Fan2016-07-144-0/+27
| | | | | | | | | | | | | | | | | | REGISTER_TYPE in UefiCpuPkg/Include/AcpiCpuData.h defines a MemoryMapped enum value. However support for the MemoryMapped enum is missing from the implementation of SetProcessorRegister(). This patch adds support for MemoryMapped type SetProcessorRegister(). One spin lock is added to avoid potential conflict when multiple processor update the same memory space. Cc: Michael Kinney <michael.d.kinney@intel.com> Cc: Feng Tian <feng.tian@intel.com> Contributed-under: TianoCore Contribution Agreement 1.0 Signed-off-by: Jeff Fan <jeff.fan@intel.com> Reviewed-by: Feng Tian <feng.tian@intel.com> Reviewed-by: Michael Kinney <michael.d.kinney@intel.com> Regression-tested-by: Laszlo Ersek <lersek@redhat.com>
* UefiCpuPkg/PiSmmCpuDxeSmm: Remove duplicate aligned buffer on S3 pathJeff Fan2016-07-141-16/+25
| | | | | | | | | | | | | | | | | | | | InitializeMpSyncData() invokes InitializeSmmCpuSemaphores() to allocate an aligned buffer for all locks and semaphores. However, this function is invoked on S3 resume path again to reset mSmmMpSyncData. It causes an additional aligned buffer to be allocated. This update moves InitializeSmmCpuSemaphores() into InitializeMpServiceData() that is only invoked on normal boot. InitializeMpSyncData() is updated to reset the locks/semaphore in mSmmMpSyncData. Cc: Michael Kinney <michael.d.kinney@intel.com> Cc: Feng Tian <feng.tian@intel.com> Contributed-under: TianoCore Contribution Agreement 1.0 Signed-off-by: Jeff Fan <jeff.fan@intel.com> Reviewed-by: Feng Tian <feng.tian@intel.com> Reviewed-by: Michael Kinney <michael.d.kinney@intel.com> Regression-tested-by: Laszlo Ersek <lersek@redhat.com>
* UefiCpuPkg/CpuMpPei: Remove PmodeOffset and LmodeOffsetJeff Fan2016-07-148-25/+17
| | | | | | | | | | | | Remove Pmode(Entry)Offset/Lmode(Entry)Offset and use unified Mode(Entry)Offset to clean up the definition of MP_ASSEMBLY_ADDRESS_MAP and MP_CPU_EXCHANGE_INFO. Cc: Feng Tian <feng.tian@intel.com> Cc: Michael Kinney <michael.d.kinney@intel.com> Cc: Giri Mudusuru <giri.p.mudusuru@intel.com> Contributed-under: TianoCore Contribution Agreement 1.0 Signed-off-by: Jeff Fan <jeff.fan@intel.com> Reviewed-by: Giri P Mudusuru <giri.p.mudusuru@intel.com>
* UefiCpuPkg/CpuMpPei: Remove un-used variables and functionsJeff Fan2016-07-148-156/+0
| | | | | | | | | Cc: Feng Tian <feng.tian@intel.com> Cc: Michael Kinney <michael.d.kinney@intel.com> Cc: Giri Mudusuru <giri.p.mudusuru@intel.com> Contributed-under: TianoCore Contribution Agreement 1.0 Signed-off-by: Jeff Fan <jeff.fan@intel.com> Reviewed-by: Giri P Mudusuru <giri.p.mudusuru@intel.com>
* UefiCpuPkg/CpuMpPei: Do not load new GDT tableJeff Fan2016-07-141-5/+1
| | | | | | | | | | | | Do not load the new GDT table and just to use the exiting BSP's GDT table set up by SEC phase. Cc: Feng Tian <feng.tian@intel.com> Cc: Michael Kinney <michael.d.kinney@intel.com> Cc: Giri Mudusuru <giri.p.mudusuru@intel.com> Contributed-under: TianoCore Contribution Agreement 1.0 Signed-off-by: Jeff Fan <jeff.fan@intel.com> Reviewed-by: Giri P Mudusuru <giri.p.mudusuru@intel.com>
* UefiCpuPkg/CpuMpPei/X64: Use CodeSegment and DataSegment fieldsJeff Fan2016-07-142-93/+71
| | | | | | | | | | | | | Using CodeSegment and DataSegment fields in ExchangeInfo instead of the hardcode MACROs for x64 arch. Switch AP from real mode to long mode directly, so needn't the CS/DS of protected mode. Cc: Feng Tian <feng.tian@intel.com> Cc: Michael Kinney <michael.d.kinney@intel.com> Cc: Giri Mudusuru <giri.p.mudusuru@intel.com> Contributed-under: TianoCore Contribution Agreement 1.0 Signed-off-by: Jeff Fan <jeff.fan@intel.com> Reviewed-by: Giri P Mudusuru <giri.p.mudusuru@intel.com>
* UefiCpuPkg/CpuMpPei/X64: Remove hard code CPU BIST valueJeff Fan2016-07-141-4/+3
| | | | | | | | | Cc: Feng Tian <feng.tian@intel.com> Cc: Michael Kinney <michael.d.kinney@intel.com> Cc: Giri Mudusuru <giri.p.mudusuru@intel.com> Contributed-under: TianoCore Contribution Agreement 1.0 Signed-off-by: Jeff Fan <jeff.fan@intel.com> Reviewed-by: Giri P Mudusuru <giri.p.mudusuru@intel.com>
* UefiCpuPkg/CpuMpPei/Ia32: Use CodeSegment and DataSegment fieldsJeff Fan2016-07-142-34/+48
| | | | | | | | | | | | Using CodeSegment and DataSegment fields in ExchangeInfo instead of the hardcode MACROs. Cc: Feng Tian <feng.tian@intel.com> Cc: Michael Kinney <michael.d.kinney@intel.com> Cc: Giri Mudusuru <giri.p.mudusuru@intel.com> Contributed-under: TianoCore Contribution Agreement 1.0 Signed-off-by: Jeff Fan <jeff.fan@intel.com> Reviewed-by: Giri P Mudusuru <giri.p.mudusuru@intel.com>
* UefiCpuPkg/CpuMpPei: Add CodeSegment and DataSegment fieldsJeff Fan2016-07-144-4/+12
| | | | | | | | | | | | Added CodeSegment and DataSegment fields in MP_CPU_EXCHANGE_INFO. They are set to the values of current BSP's CS and DS. Cc: Feng Tian <feng.tian@intel.com> Cc: Michael Kinney <michael.d.kinney@intel.com> Cc: Giri Mudusuru <giri.p.mudusuru@intel.com> Contributed-under: TianoCore Contribution Agreement 1.0 Signed-off-by: Jeff Fan <jeff.fan@intel.com> Reviewed-by: Giri P Mudusuru <giri.p.mudusuru@intel.com>
* UefiCpuPkg/CpuMpPei: Remove unnecessary variableJeff Fan2016-07-132-4/+0
| | | | | | | | | Cc: Michael Kinney <michael.d.kinney@intel.com> Cc: Feng Tian <feng.tian@intel.com> Cc: Giri P Mudusuru <giri.p.mudusuru@intel.com> Contributed-under: TianoCore Contribution Agreement 1.0 Signed-off-by: Jeff Fan <jeff.fan@intel.com> Reviewed-by: Giri P Mudusuru <giri.p.mudusuru@intel.com>
* UefiCpuPkg/CpuMpPei: Dump message if microcode signature not matchedJeff Fan2016-07-134-25/+31
| | | | | | | | | | | | | Verification microcode signature is one enhancement and not one requirement from IA32 SDM. This update is just to dump debug message instead of ASSERT() if the updated microcode signature does not match the loaded microcode signature. Cc: Michael Kinney <michael.d.kinney@intel.com> Cc: Feng Tian <feng.tian@intel.com> Cc: Giri P Mudusuru <giri.p.mudusuru@intel.com> Contributed-under: TianoCore Contribution Agreement 1.0 Signed-off-by: Jeff Fan <jeff.fan@intel.com> Reviewed-by: Giri P Mudusuru <giri.p.mudusuru@intel.com>
* UefiCpuPkg/CpuMpPei: Skip microcode check/load if it has been loadedJeff Fan2016-07-131-0/+9
| | | | | | | | | | | | | | Actually, there is only one microcode region in platform. If microcode has been loaded, its signature will not be zero and should be loaded successfully. We needn't to check microcode region and load microcode again. This update is to skip checking/loading microcode if current microcode signature is not zero. Cc: Michael Kinney <michael.d.kinney@intel.com> Cc: Feng Tian <feng.tian@intel.com> Cc: Giri P Mudusuru <giri.p.mudusuru@intel.com> Contributed-under: TianoCore Contribution Agreement 1.0 Signed-off-by: Jeff Fan <jeff.fan@intel.com> Reviewed-by: Giri P Mudusuru <giri.p.mudusuru@intel.com>
* UefiCpuPkg CpuMpPei: Update INF to refer to NASM source fileLiming Gao2016-07-111-6/+4
| | | | | | Contributed-under: TianoCore Contribution Agreement 1.0 Signed-off-by: Liming Gao <liming.gao@intel.com> Reviewed-by: Jeff Fan <jeff.fan@intel.com>
* UefiCpuPkg CpuIo2Dxe: Update INF to refer to NASM source fileLiming Gao2016-07-111-7/+5
| | | | | | Contributed-under: TianoCore Contribution Agreement 1.0 Signed-off-by: Liming Gao <liming.gao@intel.com> Reviewed-by: Jeff Fan <jeff.fan@intel.com>
* UefiCpuPkg SecCore: Update SecCore inf to refer to nasmb sourceLiming Gao2016-07-111-4/+2
| | | | | | Contributed-under: TianoCore Contribution Agreement 1.0 Signed-off-by: Liming Gao <liming.gao@intel.com> Reviewed-by: Jeff Fan <jeff.fan@intel.com>
* UefiCpuPkg: Fix typos in commentsGiri P Mudusuru2016-07-111-1/+1
| | | | | | | | | - becasue to because Cc: Jeff Fan <jeff.fan@intel.com> Contributed-under: TianoCore Contribution Agreement 1.0 Signed-off-by: Giri P Mudusuru <giri.p.mudusuru@intel.com> Reviewed-by: Jeff Fan <jeff.fan@intel.com>
* UefiCpuPkg S3Resume2Pei: Report status code when allocate memory is failedStar Zeng2016-07-021-3/+15
| | | | | | | | | Cc: Jiewen Yao <jiewen.yao@intel.com> Cc: Jeff Fan <jeff.fan@intel.com> Contributed-under: TianoCore Contribution Agreement 1.0 Signed-off-by: Star Zeng <star.zeng@intel.com> Reviewed-by: Jiewen Yao <jiewen.yao@intel.com> Reviewed-by: Jeff Fan <jeff.fan@intel.com>
* UefiCpuPkg: fix ASSERT_EFI_ERROR() typosLaszlo Ersek2016-06-301-1/+1
| | | | | | | | | | | | | | | | | | | | A number of code locations use ASSERT_EFI_ERROR (BooleanExpression) instead of ASSERT (BooleanExpression) Fix them. Cc: Jeff Fan <jeff.fan@intel.com> Reported-by: Gerd Hoffmann <kraxel@redhat.com> Contributed-under: TianoCore Contribution Agreement 1.0 Signed-off-by: Laszlo Ersek <lersek@redhat.com> Reviewed-by: Jeff Fan <jeff.fan@intel.com> Reviewed-by: Giri P Mudusuru <giri.p.mudusuru@intel.com> Reviewed-by: Michael Kinney <michael.d.kinney@intel.com>
* UefiCpuPkg PiSmmCpuDxeSmm: Add nasm source file into INF file.Liming Gao2016-06-281-26/+26
| | | | | Contributed-under: TianoCore Contribution Agreement 1.0 Signed-off-by: Liming Gao <liming.gao@intel.com>
* UefiCpuPkg PiSmmCpuDxeSmm: Convert X64/SmmInit.asm to NASMLiming Gao2016-06-281-0/+130
| | | | | | | Manually convert X64/SmmInit.asm to X64/SmmInit.nasm Contributed-under: TianoCore Contribution Agreement 1.0 Signed-off-by: Liming Gao <liming.gao@intel.com>
* UefiCpuPkg PiSmmCpuDxeSmm: Convert X64/SmiException.asm to NASMLiming Gao2016-06-281-0/+412
| | | | | | | Manually convert X64/SmiException.asm to X64/SmiException.nasm Contributed-under: TianoCore Contribution Agreement 1.0 Signed-off-by: Liming Gao <liming.gao@intel.com>
* UefiCpuPkg PiSmmCpuDxeSmm: Convert X64/SmiEntry.asm to NASMLiming Gao2016-06-281-0/+177
| | | | | | | Manually convert X64/SmiEntry.asm to X64/SmiEntry.nasm Contributed-under: TianoCore Contribution Agreement 1.0 Signed-off-by: Liming Gao <liming.gao@intel.com>
* UefiCpuPkg PiSmmCpuDxeSmm: Update X64/MpFuncs.nasmLiming Gao2016-06-281-51/+43
| | | | | | | | | | | | | | | | | | | Use 16bit and 32bit assembly code to replace hard code db. In V2: add 0x67 prefixes to far jumps Without the a32 modifier under FLAT32_JUMP, and the a16 modifier under LONG_JUMP, nasm doesn't generate the 0x67 prefixes, and the far jumps don't work. (For the former, KVM returns an emulation failure. For the latter, KVM performs a triple fault (guest reboot).) By forcing the 0x67 prefixes we end up with the same machine code as the one open-coded in "MpFuncs.asm". This bug breaks S3 resume in the Ia32X64 + SMM_REQUIRE build of OVMF. Contributed-under: TianoCore Contribution Agreement 1.0 Signed-off-by: Liming Gao <liming.gao@intel.com> Signed-off-by: Laszlo Ersek <lersek@redhat.com>
* UefiCpuPkg PiSmmCpuDxeSmm: Convert X64/MpFuncs.asm to NASMLiming Gao2016-06-281-0/+204
| | | | | | | | | The BaseTools/Scripts/ConvertMasmToNasm.py script was used to convert X64/MpFuncs.asm to X64/MpFuncs.nasm And, manually update it to pass build. Contributed-under: TianoCore Contribution Agreement 1.0 Signed-off-by: Liming Gao <liming.gao@intel.com>
* UefiCpuPkg PiSmmCpuDxeSmm: Convert Ia32/SmmInit.asm to NASMLiming Gao2016-06-281-0/+88
| | | | | | | Manually convert Ia32/SmmInit.asm to Ia32/SmmInit.nasm Contributed-under: TianoCore Contribution Agreement 1.0 Signed-off-by: Liming Gao <liming.gao@intel.com>
* UefiCpuPkg PiSmmCpuDxeSmm: Convert Ia32/SmiException.asm to NASMLiming Gao2016-06-281-0/+737
| | | | | | | Manually convert Ia32/SmiException.asm to Ia32/SmiException.nasm Contributed-under: TianoCore Contribution Agreement 1.0 Signed-off-by: Liming Gao <liming.gao@intel.com>
* UefiCpuPkg PiSmmCpuDxeSmm: Convert Ia32/SmiEntry.asm to NASMLiming Gao2016-06-281-0/+163
| | | | | | | Manually convert Ia32/SmiEntry.asm to Ia32/SmiEntry.nasm Contributed-under: TianoCore Contribution Agreement 1.0 Signed-off-by: Liming Gao <liming.gao@intel.com>
* UefiCpuPkg PiSmmCpuDxeSmm: Update Ia32/MpFuncs.nasmLiming Gao2016-06-281-26/+21
| | | | | | | | | | | | | | | | | | Use 16bit assembly code to replace hard code db. In V2: Add 0x67 prefix to far jump When we enter protected mode, with the far jump still in big real mode, the JMP instruction not only needs the 0x66 prefix (for 32-bit operand size), but also the 0x67 prefix (for 32-bit address size). Use the a32 nasm modifier to enforce this. This bug breaks S3 resume in the Ia32 + SMM_REQUIRE build of OVMF. Contributed-under: TianoCore Contribution Agreement 1.0 Signed-off-by: Liming Gao <liming.gao@intel.com> Signed-off-by: Laszlo Ersek <lersek@redhat.com>
* UefiCpuPkg PiSmmCpuDxeSmm: Convert Ia32/MpFuncs.asm to NASMLiming Gao2016-06-281-0/+164
| | | | | | | | | The BaseTools/Scripts/ConvertMasmToNasm.py script was used to convert Ia32/MpFuncs.asm to Ia32/MpFuncs.nasm. And, manually update it to pass build. Contributed-under: TianoCore Contribution Agreement 1.0 Signed-off-by: Liming Gao <liming.gao@intel.com>
* UefiCpuPkg S3Resume2Pei: Add nasm source file into INF file.Liming Gao2016-06-281-2/+4
| | | | | Contributed-under: TianoCore Contribution Agreement 1.0 Signed-off-by: Liming Gao <liming.gao@intel.com>
* UefiCpuPkg S3Resume2Pei: Convert X64/AsmFuncs.asm to NASMLiming Gao2016-06-281-0/+41
| | | | | | | | | The BaseTools/Scripts/ConvertMasmToNasm.py script was used to convert X64/AsmFuncs.asm to X64/AsmFuncs.nasm. And, manually add o16 prefix to specify 16bit operation. Contributed-under: TianoCore Contribution Agreement 1.0 Signed-off-by: Liming Gao <liming.gao@intel.com>
* UefiCpuPkg S3Resume2Pei: Convert Ia32/AsmFuncs.asm to NASMLiming Gao2016-06-281-0/+41
| | | | | | | | | The BaseTools/Scripts/ConvertMasmToNasm.py script was used to convert Ia32/AsmFuncs.asm to Ia32/AsmFuncs.nasm. And, manually add o16 prefix to specify 16bit operation. Contributed-under: TianoCore Contribution Agreement 1.0 Signed-off-by: Liming Gao <liming.gao@intel.com>
* UefiCpuPkg CpuExceptionHandlerLib: Add nasm source files into INF files.Liming Gao2016-06-283-7/+13
| | | | | Contributed-under: TianoCore Contribution Agreement 1.0 Signed-off-by: Liming Gao <liming.gao@intel.com>
* UefiCpuPkg CpuExceptionHandlerLib:Convert X64/ExceptionHandlerAsm.asm to NASMLiming Gao2016-06-281-0/+387
| | | | | | | | | The BaseTools/Scripts/ConvertMasmToNasm.py script was used to convert X64/ExceptionHandlerAsm.asm to X64/ExceptionHandlerAsm.nasm. Then, manually update nasm to pass build. Contributed-under: TianoCore Contribution Agreement 1.0 Signed-off-by: Liming Gao <liming.gao@intel.com>
* UefiCpuPkg CpuExceptionHandlerLib:Convert Ia32/ExceptionHandlerAsm.asm to NASMLiming Gao2016-06-281-0/+462
| | | | | | | | | The BaseTools/Scripts/ConvertMasmToNasm.py script was used to convert Ia32/ExceptionHandlerAsm.asm to Ia32/ExceptionHandlerAsm.nasm. Then, manually update nasm to pass build. Contributed-under: TianoCore Contribution Agreement 1.0 Signed-off-by: Liming Gao <liming.gao@intel.com>
* UefiCpuPkg BaseUefiCpuLib: Add nasm source file in BaseUefiCpuLib.infLiming Gao2016-06-281-0/+2
| | | | | Contributed-under: TianoCore Contribution Agreement 1.0 Signed-off-by: Liming Gao <liming.gao@intel.com>
* UefiCpuPkg BaseUefiCpuLib: Convert X64/InitializeFpu.asm to NASMLiming Gao2016-06-281-0/+60
| | | | | | | | | The BaseTools/Scripts/ConvertMasmToNasm.py script was used to convert X64/InitializeFpu.asm to X64/InitializeFpu.nasm. And, manually add .rdata section. Contributed-under: TianoCore Contribution Agreement 1.0 Signed-off-by: Liming Gao <liming.gao@intel.com>
* UefiCpuPkg BaseUefiCpuLib: Convert Ia32/InitializeFpu.asm to NASMLiming Gao2016-06-281-0/+74
| | | | | | | | | The BaseTools/Scripts/ConvertMasmToNasm.py script was used to convert Ia32/InitializeFpu.asm to Ia32/InitializeFpu.nasm. And, manually add .rdata section. Contributed-under: TianoCore Contribution Agreement 1.0 Signed-off-by: Liming Gao <liming.gao@intel.com>
* UefiCpuPkg CpuDxe: Add nasm source file in CpuDxe.infLiming Gao2016-06-282-13/+63
| | | | | Contributed-under: TianoCore Contribution Agreement 1.0 Signed-off-by: Liming Gao <liming.gao@intel.com>
* UefiCpuPkg CpuDxe: Convert Ia32/CpuAsm.asm to NASMLiming Gao2016-06-281-0/+53
| | | | | | | | The BaseTools/Scripts/ConvertMasmToNasm.py script was used to convert Ia32/CpuAsm.asm to Ia32/CpuAsm.nasm Contributed-under: TianoCore Contribution Agreement 1.0 Signed-off-by: Liming Gao <liming.gao@intel.com>
* UefiCpuPkg/SecMain: Decorate phase-transition function with NORETURN.Marvin H?user2016-06-221-1/+3
| | | | | | | | | | This patch adds the NORETURN attribute to the function that transfers to the PEI phase, along with an UNREACHABLE() call at the end to avoid false warnings. Contributed-under: TianoCore Contribution Agreement 1.0 Signed-off-by: Marvin Haeuser <Marvin.Haeuser@outlook.com> Reviewed-by: Liming Gao <liming.gao@intel.com>
* UefiCpuPkg/MtrrLib: Fixed bug if length is less than Fixed-MTRR rangeJeff Fan2016-06-071-23/+48
| | | | | | | | | | | | | | | | | | Currently, if the memory length to be programmed is less than the remaining size of one Fixed-MTRR supported, RETURN_UNSUPPORTED returned. This is not correct. This is one regression at 07e889209034ba94bfac9e765b8a50ef344daef2 when we updated ProgramFixedMtrr() to remove the loop of calculating Fixed-MTRR Mask. This fix will calculate Right offset in Fixed-MTRR beside left offset. It supports small length (less than remaining size supported by Fixed-MTRR) to be programmed. Cc: Eric Dong <eric.dong@intel.com> Cc: Feng Tian <feng.tian@intel.com> Cc: Michael Kinney <michael.d.kinney@intel.com> Contributed-under: TianoCore Contribution Agreement 1.0 Signed-off-by: Jeff Fan <jeff.fan@intel.com> Reviewed-by: Eric Dong <eric.dong@intel.com>
generated by cgit v1.2.3 (git 2.25.1) at 2024-08-16 18:00:33 +0000