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* UefiCpuPkg/MpInitLib: fix 32-bit build errorJian J Wang2018-01-111-1/+1
| | | | | | | | | | Cc: Dandan Bi <dandan.bi@intel.com> Cc: Eric Dong <eric.dong@intel.com> Cc: Laszlo Ersek <lersek@redhat.com> Contributed-under: TianoCore Contribution Agreement 1.1 Signed-off-by: Jian J Wang <jian.j.wang@intel.com> Reviewed-by: Eric Dong <eric.dong@intel.com> Reviewed-by: Dandan Bi <dandan.bi@intel.com>
* UefiCpuPkg/MtrrLib: Fix an assertion bugRuiyu Ni2018-01-111-1/+0
| | | | | | | | | | | | | | | | | | | | 0 40 f0 100 +---WT--+--UC--+--WT--+-----WB----+----UC----+ When calculating the shortest path from 0 to 100, the MtrrLibCalculateLeastMtrrs() is called to update the Vertices.Previous. When calculating the shortest path from 0 to 40, MtrrLibCalculateLeastMtrrs() is called recursively to update the Vertices.Previous. The second call corrupt the Previous value that will be used later. The patch removes the code that corrupts Previous. Contributed-under: TianoCore Contribution Agreement 1.1 Signed-off-by: Ruiyu Ni <ruiyu.ni@intel.com> Cc: Star Zeng <star.zeng@intel.com> Reviewed-by: Eric Dong <eric.dong@intel.com>
* UefiCpuPkg/MtrrLib: Fix a MTRR calculation bugRuiyu Ni2018-01-111-4/+5
| | | | | | | | | | | | | | | | 80 A8 B0 B8 C0 +----------WB--------+-UC-+-WT-+-WB-+ For above memory settings, current code caused the final MTRR settings miss [A8, B0, UC] when default memory type is UC. The root cause is the code only checks the mandatory weight between A8 to B0, but skips to check the optional weight. The patch fixes this issue. Contributed-under: TianoCore Contribution Agreement 1.1 Signed-off-by: Ruiyu Ni <ruiyu.ni@intel.com> Reviewed-by: Eric Dong <eric.dong@intel.com>
* UefiCpuPkg/MtrrLib: Correct typo to change vector to vertexRuiyu Ni2018-01-101-95/+95
| | | | | | | | | | The patch only change the comments and variable name so doesn't impact the functionality. Contributed-under: TianoCore Contribution Agreement 1.1 Signed-off-by: Ruiyu Ni <ruiyu.ni@intel.com> Reviewed-by: Eric Dong <eric.dong@intel.com> Cc: Star Zeng <star.zeng@intel.com>
* UefiCpuPkg/MtrrLib: Handle one setting request covering all memoryRuiyu Ni2018-01-101-1/+6
| | | | | | | | | | | *SetMemoryAttribute*() API cannot handle the setting request that looks like <0, MAX_ADDRESS, Type>. The buggy parameter checking logic returns Unsupported for this case. The patch fixes the checking logic to handle such case. Contributed-under: TianoCore Contribution Agreement 1.1 Signed-off-by: Ruiyu Ni <ruiyu.ni@intel.com> Reviewed-by: Eric Dong <eric.dong@intel.com>
* UefiCpuPkg/MtrrLib: Fix bug that may calculate wrong MTRR resultRuiyu Ni2018-01-101-12/+25
| | | | | | | | | | | | | Code forgot to initialize the optional weight between adjacent vertices. It caused wrong MTRR result was calculated for some memory settings. The logic was incorrectly removed when converting from POC code. The patch adds back the initialization. Contributed-under: TianoCore Contribution Agreement 1.1 Signed-off-by: Ruiyu Ni <ruiyu.ni@intel.com> Reviewed-by: Eric Dong <eric.dong@intel.com>
* UefiCpuPkg/MtrrLib: Refine the debug messagesRuiyu Ni2018-01-101-30/+53
| | | | | | | | | | | | | MtrrSetMemoryAttributesInMtrrSettings() missed the debug messages of memory attribute request and status. The patch moves all debug messages from MtrrSetMemoryAttributeInMtrrSettings() to MtrrSetMemoryAttributesInMtrrSettings() and refines the debug message to carry more information. Contributed-under: TianoCore Contribution Agreement 1.1 Signed-off-by: Ruiyu Ni <ruiyu.ni@intel.com> Reviewed-by: Eric Dong <eric.dong@intel.com> Cc: Star Zeng <star.zeng@intel.com>
* UefiCpuPkg/MpInitLib: fix wrong address set as Stack Guard for APsJian J Wang2018-01-101-1/+18
| | | | | | | | | | | | | | The reason is that DXE part initialization will reuse the stack allocated at PEI phase, if MP was initialized before. Some code added to check this situation and use stack base address saved in HOB passed from PEI. Cc: Jiewen Yao <jiewen.yao@intel.com> Cc: Eric Dong <eric.dong@intel.com> Cc: Laszlo Ersek <lersek@redhat.com> Contributed-under: TianoCore Contribution Agreement 1.1 Signed-off-by: Jian J Wang <jian.j.wang@intel.com> Reviewed-by: Laszlo Ersek <lersek@redhat.com> Reviewed-by: Eric Dong <eric.dong@intel.com>
* UefiCpuPkg/MpInitLib: fix incorrect stack top init for cpu0Jian J Wang2018-01-101-1/+1
| | | | | | | | | | | | | | | | As the name suggests, CpuMpData->CpuInfoInHob[0].ApTopOfStack must be init to the top of stack. But the MpInitLibInitialize() passed the base address of stack to InitializeApData(), which is not correct. Although this stack is not used for BSP, it's should be fixed in case of misunderstanding and future possible code changes. Cc: Jiewen Yao <jiewen.yao@intel.com> Cc: Eric Dong <eric.dong@intel.com> Cc: Laszlo Ersek <lersek@redhat.com> Contributed-under: TianoCore Contribution Agreement 1.1 Signed-off-by: Jian J Wang <jian.j.wang@intel.com> Reviewed-by: Laszlo Ersek <lersek@redhat.com> Reviewed-by: Eric Dong <eric.dong@intel.com>
* UefiCpuPkg/MpInitLib: Fix a bug that AP enters timer INT handlerRuiyu Ni2018-01-091-1/+5
| | | | | | | | | | When SourceLevelDebug is enabled, AP randomly executes the DXECORE timer handler logic. The root cause is the interrupts are not masked in AP wake up procedure. Contributed-under: TianoCore Contribution Agreement 1.1 Signed-off-by: Ruiyu Ni <ruiyu.ni@intel.com> Reviewed-by: Jeff Fan <vanjeff_919@hotmail.com>
* UefiCpuPkg CpuExceptionHandlerLib: Enhance DumpModuleImageInfo()Star Zeng2018-01-023-4/+22
| | | | | | | | | | | | | | | | | | | | | | | | | | Enhance DumpModuleImageInfo() for page fault with I/D set. If it is page fault with I/D set, the (E/R)IP in SystemContext could not be used for DumpModuleImageInfo(), instead of, the next IP of the IP triggering this page fault could be found from stack by (E/R)SP in SystemContext. IA32 SDM: — I/D flag (bit 4). This flag is 1 if the access causing the page-fault exception was an instruction fetch. This flag describes the access causing the page-fault exception, not the access rights specified by paging. The idea comes from SmiPFHandler () in UefiCpuPkg/PiSmmCpuDxeSmm/Ia32/PageTbl.c and UefiCpuPkg/PiSmmCpuDxeSmm/X64/PageTbl.c. Cc: Jiewen Yao <jiewen.yao@intel.com> Cc: Eric Dong <eric.dong@intel.com> Cc: Laszlo Ersek <lersek@redhat.com> Contributed-under: TianoCore Contribution Agreement 1.1 Signed-off-by: Star Zeng <star.zeng@intel.com> Reviewed-by: Jiewen Yao <jiewen.yao@intel.com>
* UefiCpuPkg: Fix comment typo for MtrrLibApplyFixedMtrrs functionSong, BinX2017-12-281-1/+1
| | | | | | | | | | Fix comment typo for MtrrLibApplyFixedMtrrs function Cc: Eric Dong <eric.dong@intel.com> Cc: Laszlo Ersek <lersek@redhat.com> Contributed-under: TianoCore Contribution Agreement 1.1 Signed-off-by: Bell Song <binx.song@intel.com> Reviewed-by: Eric Dong <eric.dong@intel.com>
* UefiCpuPkg: Rollback field name changesJian J Wang2017-12-273-16/+16
| | | | | | | | | Roll back commit 56649f43013703e95f54c293d708152b765cc49b. The original names follows the spec definition. Contributed-under: TianoCore Contribution Agreement 1.1 Signed-off-by: Jian J Wang <jian.j.wang@intel.com> Reviewed-by: Liming Gao <liming.gao@intel.com>
* UefiCpuPkg: Update AESNI support checking logicSong, BinX2017-12-271-9/+11
| | | | | | | | | | | | | | With correct model CPU, current checking logic will always execute AsmReadMsr64 operation and then check ECX.AESNI[bit 25] = 1. Update checking logic to check ECX.AESNI[bit 25] = 1 first and then do AsmReadMsr64 operation. Cc: Eric Dong <eric.dong@intel.com> Cc: Laszlo Ersek <lersek@redhat.com> Contributed-under: TianoCore Contribution Agreement 1.1 Signed-off-by: Bell Song <binx.song@intel.com> Reviewed-by: Eric Dong <eric.dong@intel.com>
* UefiCpuPkg: Delete redundant PcdGetSize PcdCpuFeaturesSupportSong, BinX2017-12-271-1/+0
| | | | | | | | | | | | | When CpuCommonFeaturesLib use RegisterCpuFeaturesLib to register CPU features, the CpuFeaturesData->BitMaskSize has already been initialized. So delete redundant PcdGetSize PcdCpuFeaturesSupport in CpuInitDataInitialize. Cc: Eric Dong <eric.dong@intel.com> Cc: Laszlo Ersek <lersek@redhat.com> Contributed-under: TianoCore Contribution Agreement 1.1 Signed-off-by: Bell Song <binx.song@intel.com> Reviewed-by: Eric Dong <eric.dong@intel.com>
* Revert "UefiCpuPkg: Check invalid RegisterCpuFeature parameter"Eric Dong2017-12-272-34/+0
| | | | | | | | | | | This reverts commit 5c59537c1092a1372913274636a8d766fdd97e61. Current code already has function IsCpuFeatureSupported to do the feature validation, not need this check logic anymore. Contributed-under: TianoCore Contribution Agreement 1.1 Signed-off-by: Bell Song <binx.song@intel.com> Reviewed-by: Eric Dong <eric.dong@intel.com>
* UefiCpuPkg: Update code to use new structure field namesJian J Wang2017-12-263-16/+16
| | | | | | | | | | | | Due to coding style fix of the structure definition in BaseLib.h, all code referencing those structure must be updated accordingly. Cc: Dandan Bi <dandan.bi@intel.com> Cc: Eric Dong <eric.dong@intel.com> Cc: Laszlo Ersek <lersek@redhat.com> Contributed-under: TianoCore Contribution Agreement 1.1 Signed-off-by: Jian J Wang <jian.j.wang@intel.com> Reviewed-by: Dandan Bi <dandan.bi@intel.com>
* UefiCpuPkg/UefiCpuPkg.uni: Add missing string definition for new PCDsJian J Wang2017-12-261-2/+14
| | | | | | | | | Cc: Dandan Bi <dandan.bi@intel.com> Cc: Eric Dong <eric.dong@intel.com> Cc: Laszlo Ersek <lersek@redhat.com> Contributed-under: TianoCore Contribution Agreement 1.1 Signed-off-by: Jian J Wang <jian.j.wang@intel.com> Reviewed-by: Dandan Bi <dandan.bi@intel.com>
* UefiCpuPkg/MpInitLib: Add missing Guard page setup for APsJian J Wang2017-12-222-3/+32
| | | | | | | | | | | | | | AP has its own stack for code execution. If PcdCpuStackGuard is enabled, the page at the bottom of stack of AP will be disabled (NOT PRESENT) to monitor the stack overflow issue. This requires PcdCpuApStackSize to be set with value more than one page of memory. Cc: Jiewen Yao <jiewen.yao@intel.com> Cc: Eric Dong <eric.dong@intel.com> Cc: Laszlo Ersek <lersek@redhat.com> Contributed-under: TianoCore Contribution Agreement 1.1 Signed-off-by: Jian J Wang <jian.j.wang@intel.com> Reviewed-by: Jiewen Yao <jiewen.yao@intel.com>
* UefiCpuPkg: Singularize function nameSong, BinX2017-12-152-28/+28
| | | | | | | | | | | Change GetSupportPcds and GetConfigurationPcds to be singular Cc: Eric Dong <eric.dong@intel.com> Cc: Laszlo Ersek <lersek@redhat.com> Contributed-under: TianoCore Contribution Agreement 1.1 Signed-off-by: Bell Song <binx.song@intel.com> Reviewed-by: Eric Dong <eric.dong@intel.com> Reviewed-by: Laszlo Ersek <lersek@redhat.com>
* UefiCpuPkg: Check invalid RegisterCpuFeature parameterSong, BinX2017-12-132-0/+34
| | | | | | | | | | | | | | V2: Update function name, add more detail description. V1: Check and assert invalid RegisterCpuFeature function parameter Cc: Eric Dong <eric.dong@intel.com> Cc: Laszlo Ersek <lersek@redhat.com> Contributed-under: TianoCore Contribution Agreement 1.1 Signed-off-by: Bell Song <binx.song@intel.com> Reviewed-by: Eric Dong <eric.dong@intel.com> Reviewed-by: Ruiyu Ni <ruiyu.ni@intel.com>
* UefiCpuPkg/CpuDxe: suppress invalid warning about uninitialized variableJian J Wang2017-12-131-0/+5
| | | | | | | | | | Cc: Eric Dong <eric.dong@intel.com> Cc: Wu Hao <hao.a.wu@intel.com> Contributed-under: TianoCore Contribution Agreement 1.1 Signed-off-by: Jian J Wang <jian.j.wang@intel.com> Reviewed-by: Eric Dong <eric.dong@intel.com> Reviewed-by: Wu Hao <hao.a.wu@intel.com> Reviewed-by: Laszlo Ersek <lersek@redhat.com>
* MdeModulePkg: Rename SmmEndOfS3ResumeProtocolGuid to EndOfS3ResumeGuidStar Zeng2017-12-122-9/+6
| | | | | | | | | | | | | | | Rename SmmEndOfS3ResumeProtocolGuid to EndOfS3ResumeGuid as the GUID may be used to install PPI in future to notify PEI phase code. The references in UefiCpuPkg are also being updated. Cc: Jiewen Yao <jiewen.yao@intel.com> Cc: Eric Dong <eric.dong@intel.com> Cc: Laszlo Ersek <lersek@redhat.com> Contributed-under: TianoCore Contribution Agreement 1.1 Signed-off-by: Star Zeng <star.zeng@intel.com> Reviewed-by: Jiewen Yao <jiewen.yao@intel.com> Reviewed-by: Laszlo Ersek <lersek@redhat.com>
* UefiCpuPkg/CpuDxe: Enable protection for newly added page tableJian J Wang2017-12-124-9/+267
| | | | | | | | | | | | | | | | | | | | | | | | | One of the functionalities of CpuDxe is to update memory paging attributes. If page table protection is applied, it must be disabled temporarily before any attributes update and enabled again afterwards. This patch makes use of the same way as DxeIpl to allocate page table memory from reserved memory pool, which helps to reduce potential "split" operation and recursive calling of SetMemorySpaceAttributes(). Laszlo (lersek@redhat.com) did a regression test on QEMU virtual platform with one middle version of this series patch. The details can be found at https://lists.01.org/pipermail/edk2-devel/2017-December/018625.html There're a few changes after his work. Cc: Jiewen Yao <jiewen.yao@intel.com> Cc: Star Zeng <star.zeng@intel.com> Cc: Eric Dong <eric.dong@intel.com> Cc: Ruiyu Ni <ruiyu.ni@intel.com> Contributed-under: TianoCore Contribution Agreement 1.1 Signed-off-by: Jian J Wang <jian.j.wang@intel.com> Reviewed-by: Jiewen Yao <jiewen.yao@intel.com>
* UefiCpuPkg/MtrrLib: Correct debug messageRuiyu Ni2017-12-111-1/+1
| | | | | | | | | | | | | | When printing the ascii format of memory attribute in debug message, %s was used, but %a should be used. The patch additionally changes %x to %r for EFI_STATUS. The whole patch doesn't impact functionality of the MtrrLib. Just debug message fix. Contributed-under: TianoCore Contribution Agreement 1.1 Signed-off-by: Ruiyu Ni <ruiyu.ni@intel.com> Reviewed-by: Eric Dong <eric.dong@intel.com> Cc: Ming Shao <ming.shao@intel.com>
* UefiCpuPkg/CpuDxe: Initialize stack switch for MPJian J Wang2017-12-082-0/+192
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | In current MP implementation, BSP and AP shares the same exception configuration. Stack switch required by Stack Guard feature needs that BSP and AP have their own configuration. This patch adds code to ask BSP and AP to do exception handler initialization separately. Since AP is not supposed to do memory allocation, all memory needed to setup stack switch will be reserved in BSP and pass to AP via new API EFI_STATUS EFIAPI InitializeCpuExceptionHandlersEx ( IN EFI_VECTOR_HANDOFF_INFO *VectorInfo OPTIONAL, IN CPU_EXCEPTION_INIT_DATA *InitData OPTIONAL ); Following two new PCDs are introduced to configure how to setup new stack for specified exception handlers. gUefiCpuPkgTokenSpaceGuid.PcdCpuStackSwitchExceptionList gUefiCpuPkgTokenSpaceGuid.PcdCpuKnownGoodStackSize Cc: Eric Dong <eric.dong@intel.com> Cc: Laszlo Ersek <lersek@redhat.com> Cc: Jiewen Yao <jiewen.yao@intel.com> Cc: Michael Kinney <michael.d.kinney@intel.com> Suggested-by: Ayellet Wolman <ayellet.wolman@intel.com> Contributed-under: TianoCore Contribution Agreement 1.1 Signed-off-by: Jian J Wang <jian.j.wang@intel.com> Reviewed-by: Jeff Fan <vanjeff_919@hotmail.com> Reviewed-by: Jiewen.yao@intel.com
* UefiCpuPkg/MpLib: Add GDTR, IDTR and TR in saved AP dataJian J Wang2017-12-082-0/+20
| | | | | | | | | | | | | | | | | | In current implementation of CPU MP service, AP is initialized with data copied from BSP. Stack switch required by Stack Guard feature needs different GDT, IDT table and task gates for each logic processor. This patch adds GDTR, IDTR and TR into structure CPU_VOLATILE_REGISTERS and related code in save and restore methods. This can make sure that any changes to GDT, IDT and task gate for an AP will be kept from overwritten by BSP settings. Cc: Eric Dong <eric.dong@intel.com> Cc: Laszlo Ersek <lersek@redhat.com> Cc: Jiewen Yao <jiewen.yao@intel.com> Suggested-by: Ayellet Wolman <ayellet.wolman@intel.com> Contributed-under: TianoCore Contribution Agreement 1.1 Signed-off-by: Jian J Wang <jian.j.wang@intel.com> Reviewed-by: Jeff Fan <vanjeff_919@hotmail.com> Reviewed-by: Jiewen.yao@intel.com
* UefiCpuPkg/CpuExceptionHandlerLib: Add stack switch supportJian J Wang2017-12-0814-3/+984
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | If Stack Guard is enabled and there's really a stack overflow happened during boot, a Page Fault exception will be triggered. Because the stack is out of usage, the exception handler, which shares the stack with normal UEFI driver, cannot be executed and cannot dump the processor information. Without those information, it's very difficult for the BIOS developers locate the root cause of stack overflow. And without a workable stack, the developer cannot event use single step to debug the UEFI driver with JTAG debugger. In order to make sure the exception handler to execute normally after stack overflow. We need separate stacks for exception handlers in case of unusable stack. IA processor allows to switch to a new stack during handling interrupt and exception. But X64 and IA32 provides different ways to make it. X64 provides interrupt stack table (IST) to allow maximum 7 different exceptions to have new stack for its handler. IA32 doesn't have IST mechanism and can only use task gate to do it since task switch allows to load a new stack through its task-state segment (TSS). The new API, InitializeCpuExceptionHandlersEx, is implemented to complete extra initialization for stack switch of exception handler. Since setting up stack switch needs allocating new memory for new stack, new GDT table and task-state segment but the initialization method will be called in different phases which have no consistent way to reserve those memory, this new API is allowed to pass the reserved resources to complete the extra works. This is cannot be done by original InitializeCpuExceptionHandlers. Considering exception handler initialization for MP situation, this new API is also necessary, because AP is not supposed to allocate memory. So the memory needed for stack switch have to be reserved in BSP before waking up AP and then pass them to InitializeCpuExceptionHandlersEx afterwards. Since Stack Guard feature is available only for DXE phase at this time, the new API is fully implemented for DXE only. Other phases implement a dummy one which just calls InitializeCpuExceptionHandlers(). Cc: Jiewen Yao <jiewen.yao@intel.com> Cc: Eric Dong <eric.dong@intel.com> Cc: Laszlo Ersek <lersek@redhat.com> Cc: Michael Kinney <michael.d.kinney@intel.com> Suggested-by: Ayellet Wolman <ayellet.wolman@intel.com> Contributed-under: TianoCore Contribution Agreement 1.1 Signed-off-by: Jian J Wang <jian.j.wang@intel.com> Reviewed-by: Jeff Fan <vanjeff_919@hotmail.com> Reviewed-by: Jiewen.yao@intel.com
* UefiCpuPkg/UefiCpuPkg.dec: Add two new PCDs for stack switchJian J Wang2017-12-081-0/+12
| | | | | | | | | | | | | | | | | | | | | | | | | Stack switch is required by Stack Guard feature. Following two PCDs are introduced to simplify the resource allocation for initializing stack switch. gUefiCpuPkgTokenSpaceGuid.PcdCpuStackSwitchExceptionList gUefiCpuPkgTokenSpaceGuid.PcdCpuKnownGoodStackSize PcdCpuStackSwitchExceptionList is used to specify which exception will have separate stack for its handler. For Stack Guard feature, #PF must be specified at least. PcdCpuKnownGoodStackSize is used to specify the size of knwon good stack for an exception handler. Cpu driver or other drivers should use this PCD to reserve new stack memory for exceptions specified by above PCD. Cc: Eric Dong <eric.dong@intel.com> Cc: Laszlo Ersek <lersek@redhat.com> Cc: Jiewen Yao <jiewen.yao@intel.com> Suggested-by: Ayellet Wolman <ayellet.wolman@intel.com> Contributed-under: TianoCore Contribution Agreement 1.1 Signed-off-by: Jian J Wang <jian.j.wang@intel.com> Reviewed-by: Jeff Fan <vanjeff_919@hotmail.com> Reviewed-by: Jiewen.yao@intel.com
* UefiCpuPkg: Update SecCore to get BFV size based on BFV header FvLengthLiming Gao2017-12-081-1/+1
| | | | | | | | | Contributed-under: TianoCore Contribution Agreement 1.1 Signed-off-by: Liming Gao <liming.gao@intel.com> Cc: Eric Dong <eric.dong@intel.com> Cc: Star Zeng <star.zeng@intel.com> Reviewed-by: Jiewen Yao <jiewen.yao@intel.com> Reviewed-by: Star Zeng <star.zeng@intel.com>
* UefiCpuPkg: SmmCpuFeaturesLib Add the missing ASM_PFX in nasm codeLiming Gao2017-12-081-3/+3
| | | | | | | | Contributed-under: TianoCore Contribution Agreement 1.1 Signed-off-by: Liming Gao <liming.gao@intel.com> Cc: Eric Dong <eric.dong@intel.com> Reviewed-by: Jiewen Yao <jiewen.yao@intel.com> Reviewed-by: Eric Dong <eric.dong@intel.com>
* UefiCpuPkg: PiSmmCpuDxeSmm Add the missing ASM_PFX in nasm codeLiming Gao2017-12-081-5/+5
| | | | | | | Contributed-under: TianoCore Contribution Agreement 1.1 Signed-off-by: Liming Gao <liming.gao@intel.com> Reviewed-by: Jiewen Yao <jiewen.yao@intel.com> Reviewed-by: Eric Dong <eric.dong@intel.com>
* UefiCpuPkg PiSmmCpuDxeSmm: SMM profile and static paging mutual exclusionStar Zeng2017-12-084-9/+35
| | | | | | | | | | | | | | | | | | SMM profile and static paging could not be enabled at the same time, this patch is to add check and comments to make sure it. Similar comments are also added for the case of static paging and heap guard for SMM. Cc: Jiewen Yao <jiewen.yao@intel.com> Cc: Eric Dong <eric.dong@intel.com> Cc: Ruiyu Ni <ruiyu.ni@intel.com> Cc: Jian J Wang <jian.j.wang@intel.com> Cc: Laszlo Ersek <lersek@redhat.com> Contributed-under: TianoCore Contribution Agreement 1.1 Signed-off-by: Star Zeng <star.zeng@intel.com> Reviewed-by: Eric Dong <eric.dong@intel.com> Reviewed-by: Laszlo Ersek <lersek@redhat.com>
* UefiCpuPkg PiSmmCpuDxeSmm: Only DumpCpuContext in error caseStar Zeng2017-12-082-4/+8
| | | | | | | | | | | | | | | | | | Only DumpCpuContext in error case, otherwise there will be too many debug messages from DumpCpuContext() when SmmProfile feature is enabled by setting PcdCpuSmmProfileEnable to TRUE. Those debug messages are not needed for SmmProfile feature as it will record those information to buffer for further dump. Cc: Jiewen Yao <jiewen.yao@intel.com> Cc: Eric Dong <eric.dong@intel.com> Cc: Laszlo Ersek <lersek@redhat.com> Cc: Ruiyu Ni <ruiyu.ni@intel.com> Contributed-under: TianoCore Contribution Agreement 1.1 Signed-off-by: Star Zeng <star.zeng@intel.com> Reviewed-by: Jiewen Yao <jiewen.yao@intel.com> Reviewed-by: Eric Dong <eric.dong@intel.com> Acked-by: Laszlo Ersek <lersek@redhat.com>
* IntelSiliconPkg: Move MicrocodeUpdate from UefiCpuPkgStar Zeng2017-11-3020-2723/+0
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | REF: https://bugzilla.tianocore.org/show_bug.cgi?id=540 To consume FIT table for Microcode update, UefiCpuPkg/Feature/Capsule/MicrocodeUpdateDxe needs to be updated to consume IntelSiliconPkg/Include/IndustryStandard/FirmwareInterfaceTable.h, but UefiCpuPkg could not depend on IntelSiliconPkg. Since the Microcode update feature is specific to Intel, we can first move the Microcode update feature code from UefiCpuPkg to IntelSiliconPkg [first step], then update the code to consume FIT table [second step]. This patch series is for the first step. Note: No any code change in this patch, just move. Next patch will update MicrocodeUpdate to build with the package. Cc: Jiewen Yao <jiewen.yao@intel.com> Cc: Michael D Kinney <michael.d.kinney@intel.com> Cc: Eric Dong <eric.dong@intel.com> Cc: Laszlo Ersek <lersek@redhat.com> Regression-tested-by: Yonghong Zhu <yonghong.zhu@intel.com> Contributed-under: TianoCore Contribution Agreement 1.1 Signed-off-by: Star Zeng <star.zeng@intel.com> Reviewed-by: Jiewen Yao <jiewen.yao@intel.com> Reviewed-by: Eric Dong <eric.dong@intel.com> Acked-by: Laszlo Ersek <lersek@redhat.com>
* UefiCpuPkg/CpuDxe: Fix multiple entries of RT_CODE in memory mapJian J Wang2017-11-241-21/+73
| | | | | | | | | | | | | | | | | | | | | | | | More than one entry of RT_CODE memory might cause boot problem for some old OSs. This patch will fix this issue to keep OS compatibility as much as possible. More detailed information, please refer to https://bugzilla.tianocore.org/show_bug.cgi?id=753 Laszlo did a thorough test on OVMF emulated platform. The details can be found at https://bugzilla.tianocore.org/show_bug.cgi?id=753#c10 Cc: Eric Dong <eric.dong@intel.com> Cc: Jiewen Yao <jiewen.yao@intel.com> Cc: Star Zeng <star.zeng@intel.com> Cc: Laszlo Ersek <lersek@redhat.com> Cc: Ard Biesheuvel <ard.biesheuvel@linaro.org> Contributed-under: TianoCore Contribution Agreement 1.1 Signed-off-by: Jian J Wang <jian.j.wang@intel.com> Tested-by: Laszlo Ersek <lersek@redhat.com> Reviewed-by: Star Zeng <star.zeng@intel.com> Reviewed-by: Laszlo Ersek <lersek@redhat.com>
* UefiCpuPkg: Fix unix style of EOLJian J Wang2017-11-217-309/+309
| | | | | | | | | Cc: Wu Hao <hao.a.wu@intel.com> Cc: Star Zeng <star.zeng@intel.com> Cc: Eric Dong <eric.dong@intel.com> Contributed-under: TianoCore Contribution Agreement 1.1 Signed-off-by: Jian J Wang <jian.j.wang@intel.com> Reviewed-by: Hao Wu <hao.a.wu@intel.com>
* UefiCpuPkg/ResetVector/Vtf0: document segment register setupLaszlo Ersek2017-11-172-0/+11
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | "Main.asm" calls TransitionFromReal16To32BitFlat (and does some other things) before it jumps to the platform's SEC entry point. TransitionFromReal16To32BitFlat enters big real mode, and sets the DS, ES, FS, GS, and SS registers to offset ("selector") LINEAR_SEL in the GDT (defined in "UefiCpuPkg/ResetVector/Vtf0/Ia16/Real16ToFlat32.asm"). The GDT entry ("segment descriptor") at LINEAR_SEL defines a segment covering the full 32-bit address space, meant for "read/write data". Document this fact for all the affected segment registers, as output parameters for TransitionFromReal16To32BitFlat, saying "Selector allowing flat access to all addresses". For 64-bit SEC, "Main.asm" calls Transition32FlatTo64Flat in addition, between calling TransitionFromReal16To32BitFlat and jumping to the SEC entry point. Transition32FlatTo64Flat enters long mode. In long mode, segmentation is largely ignored: - all segments are considered flat (covering the whole 64-bit address space), - with the (possible) exception of FS and GS, whose bases can still be changed, albeit with new methods, not through the GDT. (Through the IA32_FS_BASE and IA32_GS_BASE Model Specific Registers, and/or the WRFSBASE, WRGSBASE and SWAPGS instructions.) Thus, document the segment registers with the same "Selector allowing flat access to all addresses" language on the "Main.asm" level too, since that is valid for both 32-bit and 64-bit modes. (Technically, "Main.asm" does not return, but RBP/EBP, passed similarly to the SEC entry point, is already documented as an output parameter.) Cc: Ard Biesheuvel <ard.biesheuvel@linaro.org> Cc: Eric Dong <eric.dong@intel.com> Cc: Jordan Justen <jordan.l.justen@intel.com> Suggested-by: Jordan Justen <jordan.l.justen@intel.com> Contributed-under: TianoCore Contribution Agreement 1.1 Signed-off-by: Laszlo Ersek <lersek@redhat.com> Acked-by: Ard Biesheuvel <ard.biesheuvel@linaro.org> Reviewed-by: Jordan Justen <jordan.l.justen@intel.com>
* UefiCpuPkg/PiSmmCpuDxeSmm: Add SmmMemoryAttribute protocolJian J Wang2017-11-176-1/+307
| | | | | | | | | | | | | | | | | | | | | | | | | | | Heap guard makes use of paging mechanism to implement its functionality. But there's no protocol or library available to change page attribute in SMM mode. A new protocol gEdkiiSmmMemoryAttributeProtocolGuid is introduced to make it happen. This protocol provide three interfaces struct _EDKII_SMM_MEMORY_ATTRIBUTE_PROTOCOL { EDKII_SMM_GET_MEMORY_ATTRIBUTES GetMemoryAttributes; EDKII_SMM_SET_MEMORY_ATTRIBUTES SetMemoryAttributes; EDKII_SMM_CLEAR_MEMORY_ATTRIBUTES ClearMemoryAttributes; }; Since heap guard feature need to update page attributes. The page table should not set to be read-only if heap guard feature is enabled for SMM mode. Otherwise this feature cannot work. Cc: Eric Dong <eric.dong@intel.com> Cc: Jiewen Yao <jiewen.yao@intel.com> Cc: Laszlo Ersek <lersek@redhat.com> Cc: Ruiyu Ni <ruiyu.ni@intel.com> Suggested-by: Ayellet Wolman <ayellet.wolman@intel.com> Contributed-under: TianoCore Contribution Agreement 1.1 Signed-off-by: Jian J Wang <jian.j.wang@intel.com> Reviewed-by: Jiewen Yao <jiewen.yao@intel.com> Regression-tested-by: Laszlo Ersek <lersek@redhat.com>
* UefiCpuPkg/CpuDxe: Reduce debug messageJian J Wang2017-11-171-2/+2
| | | | | | | | | | | | | | | Heap guard feature will frequently update page attributes. The debug message in CpuDxe driver will slow down the boot performance noticeably. Changing the debug level to DEBUG_VERBOSE to reduce the message output for normal debug configuration. Cc: Eric Dong <eric.dong@intel.com> Cc: Jiewen Yao <jiewen.yao@intel.com> Suggested-by: Ayellet Wolman <ayellet.wolman@intel.com> Contributed-under: TianoCore Contribution Agreement 1.1 Signed-off-by: Jian J Wang <jian.j.wang@intel.com> Reviewed-by: Jiewen Yao <jiewen.yao@intel.com> Regression-tested-by: Laszlo Ersek <lersek@redhat.com>
* UefiCpuPkg/MpInitLib:Make function comments align with functionDandan Bi2017-11-021-1/+1
| | | | | | | Cc: Eric Dong <eric.dong@intel.com> Contributed-under: TianoCore Contribution Agreement 1.1 Signed-off-by: Dandan Bi <dandan.bi@intel.com> Reviewed-by: Eric Dong <eric.dong@intel.com>
* UefiCpuPkg/MpInitLib: Keep compatible with former AP counting solution.Eric Dong2017-10-271-8/+13
| | | | | | | | | | | | | | | | | | | | For some special platforms (such as Ovmf), it is possible that, some APs start up *and finish* before the remaining APs start up *at all*. In this case, the enhance solution by changes 0594ec41 not works as expected. This change remove check CpuMpData->CpuCount logic to let old solution still workable if platform owner still set a long time for PcdCpuApInitTimeOutInMicroSeconds. It's platform owner's response to decide which solution to use. Cc: Ruiyu Ni <ruiyu.ni@intel.com> Cc: Laszlo Ersek <lersek@redhat.com> Cc: Jeff Fan <vanjeff_919@hotmail.com> Contributed-under: TianoCore Contribution Agreement 1.1 Signed-off-by: Eric Dong <eric.dong@intel.com> Reviewed-by: Laszlo Ersek <lersek@redhat.com> Reviewed-by: Jeff Fan <vanjeff_919@hotmail.com>
* UefiCpuPkg/CpuFeatures: Export HOB if CPU initialized in PEIEric Dong2017-10-274-0/+28
| | | | | | | | | | | | | | | | | | | | | | | | In current implementation, CPU initialized can be done in PEI or DXE phase. PEI uses CpuFeaturesPei and Dxe uses CpuFeaturesDxe. If CPU initialized in PEI phase, CpuFeaturesDxe driver will not be used. This driver will install gEdkiiCpuFeaturesInitDoneGuid protocol after it initializes the CPU. Some drivers depend on this protocol to dispatch themselves. If CpuFeaturesDxe not been used, these drivers will not be dispatched. This patch fix the above issue. If Cpu initialized in PEI phase, it also report a guid HOB for CpuFeaturesDxe. CpuFeaturesDxe will check this HOB first. If it found this HOB, it just install gEdkiiCpuFeaturesInitDoneGuid protocol, else it will also do the CPU initialization. Cc: Ruiyu Ni <ruiyu.ni@intel.com> Cc: Laszlo Ersek <lersek@redhat.com> Contributed-under: TianoCore Contribution Agreement 1.1 Signed-off-by: Eric Dong <eric.dong@intel.com> Reviewed-by: Ruiyu Ni <ruiyu.ni@intel.com> Reviewed-by: Laszlo Ersek <lersek@redhat.com>
* UefiCpuPkg/MpInitLib: Enhance waiting for AP initialization logic.Eric Dong2017-10-246-7/+30
| | | | | | | | | | | | | | | | | Current logic always waiting for a specific value to collect all APs count. This logic may caused some platforms cost too much time to wait for time out. This patch add new logic to collect APs count. It adds new variable NumApsExecuting to detect whether all APs have finished initialization. Each AP let NumApsExecuting++ when begin to initialize itself and let NumApsExecuting-- when it finish the initialization. BSP base on whether NumApsExecuting == 0 to finished the collect AP process. Cc: Ruiyu Ni <ruiyu.ni@intel.com> Contributed-under: TianoCore Contribution Agreement 1.1 Signed-off-by: Eric Dong <eric.dong@intel.com> Reviewed-by: Ruiyu Ni <ruiyu.ni@intel.com> Reviewed-by: Jeff Fan <vanjeff_919@hotmail.com>
* UefiCpuPkg/MpInitLib: Change AP Index variable name.Eric Dong2017-10-246-10/+10
| | | | | | | | | | | | Original AP index variable name not well express the meaning of the variable. Also this name is better used in later patch. So change the variable name for better understanding. Cc: Ruiyu Ni <ruiyu.ni@intel.com> Contributed-under: TianoCore Contribution Agreement 1.1 Signed-off-by: Eric Dong <eric.dong@intel.com> Reviewed-by: Ruiyu Ni <ruiyu.ni@intel.com> Reviewed-by: Jeff Fan <vanjeff_919@hotmail.com>
* UefiCpuPkg/MtrrLib: Make comments align with functionDandan Bi2017-10-242-2/+2
| | | | | | | | Cc: Eric Dong <eric.dong@intel.com> Cc: Ruiyu Ni <ruiyu.ni@intel.com> Contributed-under: TianoCore Contribution Agreement 1.1 Signed-off-by: Dandan Bi <dandan.bi@intel.com> Reviewed-by: Ruiyu Ni <ruiyu.ni@intel.com>
* UefiCpuPkg/MtrrLib: Use SetMem instead of SetMem64 to fix hangRuiyu Ni2017-10-231-2/+2
| | | | | | | | | | | ClearMasks and OrMasks are not 8-byte aligned. But SetMem64 requires the input address is 8-byte aligned. If the input is not 8-byte aligned, assertion is hit. Use SetMem instead. Contributed-under: TianoCore Contribution Agreement 1.1 Signed-off-by: Ruiyu Ni <ruiyu.ni@intel.com> Reviewed-by: Eric Dong <eric.dong@intel.com>
* UefiCpuPkg/MtrrLib: Fix bug that may incorrectly set <1MB attributeRuiyu Ni2017-10-201-4/+15
| | | | | | | | | | | | | | | | MtrrLibSetBelow1MBMemoryAttribute() may be called multiple times. It's possible that in a 2nd call, Modified[0] is set to TRUE in 1st call but ClearMasks[0] and OrMasks[0] is uninitialized in 2nd call. It causes FixedSettings->Mtrr[0] be set to random data. The patch fixes this issue by introducing a local Modified[] array and only updates FixedSettings->Mtrr[] when LocalModified[i] is TRUE. Contributed-under: TianoCore Contribution Agreement 1.1 Signed-off-by: Ruiyu Ni <ruiyu.ni@intel.com> Reviewed-by: Hao A Wu <hao.a.wu@intel.com>
* UefiCpuPkg/MpInitLib: Avoid call PcdGet* in Ap & Bsp.Eric Dong2017-10-203-8/+8
| | | | | | | | | | | | | | | | | | | | | | MicrocodeDetect function will run by every threads, and it will use PcdGet to get PcdCpuMicrocodePatchAddress and PcdCpuMicrocodePatchRegionSize, if change both PCD default to dynamic, system will in non-deterministic behavior. By design, UEFI/PI services are single threaded and not re-entrant so Multi processor code should not use UEFI/PI services. Here, Pcd protocol/PPI is used to access dynamic PCDs so it would result in non-deterministic behavior. This code get PCD value in BSP and save them in CPU_MP_DATA for Ap. https://bugzilla.tianocore.org/show_bug.cgi?id=726 Cc: Crystal Lee <CrystalLee@ami.com.tw> Cc: Ruiyu Ni <ruiyu.ni@intel.com> Contributed-under: TianoCore Contribution Agreement 1.1 Signed-off-by: Eric Dong <eric.dong@intel.com> Reviewed-by: Ruiyu Ni <ruiyu.ni@intel.com>
* UefiCpuPkg/MtrrLib: Fix MtrrDebugPrintAllMtrrsWorker to avoid hangRuiyu Ni2017-10-171-3/+6
| | | | | | | | | | | | | | | ARRAY_SIZE(Mtrrs->Variables.Mtrr) was used in MtrrDebugPrintAllMtrrsWorker() to parse the MTRR registers. Instead, the actual variable MTRR count should be used. Otherwise, the uninitialized random data in MtrrSetting may cause MtrrLibSetMemoryType() hang. Steven Shi found this bug in QEMU when using Q35 chip. Contributed-under: TianoCore Contribution Agreement 1.1 Signed-off-by: Ruiyu Ni <ruiyu.ni@intel.com> Reviewed-by: Steven Shi <steven.shi@intel.com> Cc: Laszlo Ersek <lersek@redhat.com>
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