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* UefiCpuPkg/PiSmmCpuDxeSmm: Add support for PCD ↵Leo Duran2017-03-019-125/+91
| | | | | | | | | | | | | | | | | | | PcdPteMemoryEncryptionAddressOrMask This PCD holds the address mask for page table entries when memory encryption is enabled on AMD processors supporting the Secure Encrypted Virtualization (SEV) feature. The mask is applied when page tables entriees are created or modified. CC: Jeff Fan <jeff.fan@intel.com> Cc: Feng Tian <feng.tian@intel.com> Cc: Star Zeng <star.zeng@intel.com> Cc: Laszlo Ersek <lersek@redhat.com> Cc: Brijesh Singh <brijesh.singh@amd.com> Contributed-under: TianoCore Contribution Agreement 1.0 Signed-off-by: Leo Duran <leo.duran@amd.com> Reviewed-by: Jeff Fan <jeff.fan@intel.com>
* UefiCpuPkg/Universal/Acpi/S3Resume2Pei: Add support for PCD ↵Leo Duran2017-03-012-4/+15
| | | | | | | | | | | | | | | | | | | PcdPteMemoryEncryptionAddressOrMask This PCD holds the address mask for page table entries when memory encryption is enabled on AMD processors supporting the Secure Encrypted Virtualization (SEV) feature. The mask is applied when page tables are created (S3Resume.c). CC: Jeff Fan <jeff.fan@intel.com> Cc: Feng Tian <feng.tian@intel.com> Cc: Star Zeng <star.zeng@intel.com> Cc: Laszlo Ersek <lersek@redhat.com> Cc: Brijesh Singh <brijesh.singh@amd.com> Contributed-under: TianoCore Contribution Agreement 1.0 Signed-off-by: Leo Duran <leo.duran@amd.com> Reviewed-by: Jeff Fan <jeff.fan@intel.com>
* UefiCpuPkg/CpuDxe: Do not ASSERT on AllocateMemorySpace() errorJeff Fan2017-02-271-1/+9
| | | | | | | | | | | | | | | | | | | | | | | Platform PEI may add LOCAL APIC memory mapped space into EFI_HOB_MEMORY_ALLOCATION. Or platform may allocate this range before. So, we skip AllocateMemorySpace()'s return status checking. Instead, we add one DEBUG message for possible trace. https://bugzilla.tianocore.org/show_bug.cgi?id=390 This updating is suggested by Ersek's comments at https://www.mail-archive.com/edk2-devel@lists.01.org/msg22585.html Cc: Laszlo Ersek <lersek@redhat.com> Cc: Star Zeng <star.zeng@intel.com> Cc: Feng Tian <feng.tian@intel.com> Cc: Michael D Kinney <michael.d.kinney@intel.com> Contributed-under: TianoCore Contribution Agreement 1.0 Signed-off-by: Jeff Fan <jeff.fan@intel.com> Reviewed-by: Feng Tian <feng.tian@intel.com> Reviewed-by: Star Zeng <star.zeng@intel.com> Reviewed-by: Laszlo Ersek <lersek@redhat.com>
* UefiCpuPkg/CpuDxe: Replace EFI_D_xxx with DEBUG_xxx in DEBUG()Jeff Fan2017-02-242-7/+7
| | | | | | | | | | Cc: Laszlo Ersek <lersek@redhat.com> Cc: Feng Tian <feng.tian@intel.com> Cc: Michael D Kinney <michael.d.kinney@intel.com> Contributed-under: TianoCore Contribution Agreement 1.0 Signed-off-by: Jeff Fan <jeff.fan@intel.com> Reviewed-by: Feng Tian <feng.tian@intel.com> Reviewed-by: Laszlo Ersek <lersek@redhat.com>
* UefiCpuPkg/CpuDxe: Fix hard code actual TimerPeriod valueJeff Fan2017-02-223-3/+25
| | | | | | | | | | | | | | | Current CpuGetTimerValue() implementation return hard code TimerPeriod value. We could calculate the actual TimerPeriod value over period of time (100us) at the first time invoking CpuGetTimerValue() and save the TimerPeriod value into one global variable to avoid delay at the next CpuGetTimerValue() invoking. https://bugzilla.tianocore.org/show_bug.cgi?id=382 Cc: Feng Tian <feng.tian@intel.com> Cc: Michael D Kinney <michael.d.kinney@intel.com> Contributed-under: TianoCore Contribution Agreement 1.0 Signed-off-by: Jeff Fan <jeff.fan@intel.com> Reviewed-by: Feng Tian <feng.tian@Intel.com>
* UefiCpuPkg/CpuDxe: Add Local APIC memory mapped space in GCDJeff Fan2017-02-221-0/+35
| | | | | | | | | | | | | | | | | | | | | Local APIC memory mapped space should be added into GCD and be allocated. Otherwise, UEFI firmware cannot get correct memory map for it. For example, SMM profile feature needs to get the completed MMIO map to protect them. v2: Consume AddMemoryMappedIoSpace() to handle the case that Local APIC memory space has already been added before. https://bugzilla.tianocore.org/show_bug.cgi?id=390 Cc: Laszlo Ersek <lersek@redhat.com> Cc: Jiewen Yao <jiewen.yao@intel.com> Cc: Feng Tian <feng.tian@intel.com> Cc: Michael D Kinney <michael.d.kinney@intel.com> Contributed-under: TianoCore Contribution Agreement 1.0 Signed-off-by: Jeff Fan <jeff.fan@intel.com> Reviewed-by: Laszlo Ersek <lersek@redhat.com> Regression-tested-by: Laszlo Ersek <lersek@redhat.com>
* UefiCpuPkg/CpuDxe: Copy two functions from PciHostBridgeJeff Fan2017-02-221-0/+148
| | | | | | | | | | | | | | | | Copy AddMemoryMappedIoSpace() and IntersectMemoryDescriptor() from MdeModulePkg\Bus\Pci\PciHostBridgeDxe\PciHostBridge.c. https://bugzilla.tianocore.org/show_bug.cgi?id=390 Cc: Laszlo Ersek <lersek@redhat.com> Cc: Jiewen Yao <jiewen.yao@intel.com> Cc: Feng Tian <feng.tian@intel.com> Cc: Michael D Kinney <michael.d.kinney@intel.com> Contributed-under: TianoCore Contribution Agreement 1.0 Signed-off-by: Jeff Fan <jeff.fan@intel.com> Reviewed-by: Laszlo Ersek <lersek@redhat.com> Regression-tested-by: Laszlo Ersek <lersek@redhat.com>
* UefiCpuPkg/CpuDxe: Add memory attribute setting.Jiewen Yao2017-02-224-61/+977
| | | | | | | | | | | | | | Add memory attribute setting in CpuArch protocol. Previous SetMemoryAttributes() API only supports cache attribute setting. This patch updated SetMemoryAttributes() API to support memory attribute setting by updating CPU page table. Cc: Jeff Fan <jeff.fan@intel.com> Cc: Michael Kinney <michael.d.kinney@intel.com> Contributed-under: TianoCore Contribution Agreement 1.0 Signed-off-by: Jiewen Yao <jiewen.yao@intel.com> Reviewed-by: Jeff Fan <jeff.fan@intel.com>
* UefiCpuPkg/ExceptionHandlerAsm.S: Fix code length issue with GCC 5.4Jeff Fan2017-02-221-2/+3
| | | | | | | | | | | | | | | | | | | | | | | X64\ExceptionHandlerAsm.S define MARCO to set up 32 IDT entries header. It assume GCC compiler will generate the same code length on the following instrction for each IDT entry. jmp ASM_PFX(CommonInterruptEntry) It works with GCC 4.x. However, GCC 5.4 will generate different code size of IDT entry code per the offset value from CommonInterruptEntry address. We should use DB to make sure each IDT entry header has the same size whatever compiler version. .ASM and .nasm used the different solution and do not have this issue. https://bugzilla.tianocore.org/show_bug.cgi?id=389 Cc: Liming Gao <liming.gao@intel.com> Cc: Feng Tian <feng.tian@intel.com> Cc: Michael D Kinney <michael.d.kinney@intel.com> Contributed-under: TianoCore Contribution Agreement 1.0 Signed-off-by: Jeff Fan <jeff.fan@intel.com> Reviewed-by: Liming Gao <liming.gao@intel.com>
* UefiCpuPkg: Modify CpuIoPei to support new IoLib libraryLeo Duran2017-01-171-0/+52
| | | | | | | | | | | | | The IO_PPI supports Fifo types by invoking the Fifo routines in the new BaseIoLibIntrinsic (IoLib class) library. Cc: Jeff Fan <jeff.fan@intel.com> Contributed-under: TianoCore Contribution Agreement 1.0 Signed-off-by: Brijesh Singh <brijesh.singh@amd.com> Signed-off-by: Leo Duran <leo.duran@amd.com> Reviewed-by: Liming Gao <liming.gao@intel.com> Reviewed-by: Jordan Justen <jordan.l.justen@intel.com> Reviewed-by: Jeff Fan <jeff.fan@intel.com>
* UefiCpuPkg: Modify CpuIo2Dxe to use new IoLib libraryLeo Duran2017-01-177-717/+10
| | | | | | | | | | | | | The Fifo routines from the UefiCpuPkg/CpuIo2Dxe driver have been moved to the new BaseIoLibIntrinsic (IoLib class) library. Cc: Jeff Fan <jeff.fan@intel.com> Contributed-under: TianoCore Contribution Agreement 1.0 Signed-off-by: Brijesh Singh <brijesh.singh@amd.com> Signed-off-by: Leo Duran <leo.duran@amd.com> Reviewed-by: Liming Gao <liming.gao@intel.com> Reviewed-by: Jordan Justen <jordan.l.justen@intel.com> Reviewed-by: Jeff Fan <jeff.fan@intel.com>
* UefiCpuPkg/MpInitLib: Add missing point markJeff Fan2017-01-161-1/+1
| | | | | | | Cc: Dandan Bi <dandan.bi@intel.com> Contributed-under: TianoCore Contribution Agreement 1.0 Signed-off-by: Jeff Fan <jeff.fan@intel.com> Reviewed-by: Dandan Bi <dandan.bi@intel.com>
* UefiCpuPkg/MpInitLib: Set initialize value of TimerPeriodJeff Fan2016-12-301-0/+1
| | | | | | | | | | This fix is to pass VS2010/VS2012 build. Cc: Feng Tian <feng.tian@intel.com> Cc: Dandan Bi <dandan.bi@intel.com> Contributed-under: TianoCore Contribution Agreement 1.0 Signed-off-by: Jeff Fan <jeff.fan@intel.com> Reviewed-by: Dandan Bi <dandan.bi@intel.com>
* UefiCpuPkg/MpInitLib: Set new AP to idle state after switching BSPJeff Fan2016-12-281-0/+2
| | | | | | | | | | | | We need to set new AP to idle state if it is expected to be waken up by new BSP later. Cc: Feng Tian <feng.tian@intel.com> Cc: Kinney Michael D <michael.d.kinney@intel.com> Cc: Ruiyu Ni <ruiyu.ni@intel.com> Contributed-under: TianoCore Contribution Agreement 1.0 Signed-off-by: Jeff Fan <jeff.fan@intel.com> Reviewed-by: Feng Tian <feng.tian@intel.com>
* UefiCpuPkg/MpInitLib: Disable and restore system timer interruptJeff Fan2016-12-282-1/+33
| | | | | | | | | | | | We need to disable system timer interrup to avoid generating the pending interrupt on the old BSP. Cc: Feng Tian <feng.tian@intel.com> Cc: Kinney Michael D <michael.d.kinney@intel.com> Cc: Ruiyu Ni <ruiyu.ni@intel.com> Contributed-under: TianoCore Contribution Agreement 1.0 Signed-off-by: Jeff Fan <jeff.fan@intel.com> Reviewed-by: Feng Tian <feng.tian@intel.com>
* UefiCpuPkg/MpInitLib: Swap local APIC timer interrupt stateJeff Fan2016-12-281-0/+9
| | | | | | | | | | | We need to swap local APIC timer interrupt state between old BSP and new BSP. Cc: Feng Tian <feng.tian@intel.com> Cc: Kinney Michael D <michael.d.kinney@intel.com> Cc: Ruiyu Ni <ruiyu.ni@intel.com> Contributed-under: TianoCore Contribution Agreement 1.0 Signed-off-by: Jeff Fan <jeff.fan@intel.com> Reviewed-by: Feng Tian <feng.tian@intel.com>
* UefiCpuPkg/MpInitLib: Move save/restore interrupt to SwitchBSPWorker()Jeff Fan2016-12-282-19/+21
| | | | | | | | | | | | | | | During switching BSP phase, we need to disable CPU interruput to prevent stack crashed by Timer interrupt handle. But when we enabled source debugging feature, debug timer interrupt handler (existing on both PEI and DXE) also could crash the stack used during switching BSP. So,we need to move save/restore interrupt to SwitchBSPWorker(). Cc: Feng Tian <feng.tian@intel.com> Cc: Kinney Michael D <michael.d.kinney@intel.com> Cc: Ruiyu Ni <ruiyu.ni@intel.com> Contributed-under: TianoCore Contribution Agreement 1.0 Signed-off-by: Jeff Fan <jeff.fan@intel.com> Reviewed-by: Feng Tian <feng.tian@intel.com>
* UefiCpuPkg/MpInitLib: Sync BSP's local APIC timer settings to APsJeff Fan2016-12-282-1/+60
| | | | | | | | | | | | | | | | | | | If APs are waken up by INIT-SIPI-SIPI command, they will lose original local APIC timer setting. As a result, the timer library instance based on local APIC timer cannot work on APs function. This fix is to save BSP's local APIC timer settings before waking up APs and to sync to APs when APs wakeup by INIT-SIPI-SIPI command. Setting BSP's current counter to AP's initial counter could make sure BSP and APs have same counter value across BSP switching. Cc: Feng Tian <feng.tian@intel.com> Cc: Kinney Michael D <michael.d.kinney@intel.com> Cc: Ruiyu Ni <ruiyu.ni@intel.com> Contributed-under: TianoCore Contribution Agreement 1.0 Signed-off-by: Jeff Fan <jeff.fan@intel.com> Reviewed-by: Feng Tian <feng.tian@intel.com>
* UefiCpuPkg/DxeMpInitLib: Support source debugging on AP functionJeff Fan2016-12-285-0/+43
| | | | | | | | | | | | | | | | | | The current DxeDebugAgentLib supports source debugging on AP function. This update is to update DxeMpInitLib to consume Debug Agent Library by DEBUG_AGENT_INIT_DXE_AP flag. Thus, we could source debugging AP function invoked by CPU MP Protocol. However, current SecPeiDebugAgentLib does not support source debugging on AP function invoked by CPU MP PPI. I have submitted one bugzilla to add this support at https://bugzilla.tianocore.org/show_bug.cgi?id=308. Cc: Feng Tian <feng.tian@intel.com> Cc: Kinney Michael D <michael.d.kinney@intel.com> Cc: Ruiyu Ni <ruiyu.ni@intel.com> Contributed-under: TianoCore Contribution Agreement 1.0 Signed-off-by: Jeff Fan <jeff.fan@intel.com> Reviewed-by: Feng Tian <feng.tian@intel.com>
* UefiCpuPkg/MicrocodeUpdate: Add MP support.Jiewen Yao2016-12-284-161/+476
| | | | | | | | | | | | | Support the case that BSP and AP are using different Microcode. The previous logic validates new MCU on BSP only. The enhanced logic will validate MCU on every BSP and AP. As long as one processor loads the MCU successfully, it will be updated. Cc: Jeff Fan <jeff.fan@intel.com> Cc: Star Zeng <star.zeng@intel.com> Contributed-under: TianoCore Contribution Agreement 1.0 Signed-off-by: Jiewen Yao <jiewen.yao@intel.com> Reviewed-by: Jeff Fan <jeff.fan@intel.com>
* UefiCpuPkg/MicrocodeUpdate: enhance flash write logicJiewen Yao2016-12-283-316/+492
| | | | | | | | | | | | | | | | | The patch updated MicrocodeWrite() to move the Microcode replacement logic to a standalone function - UpdateMicrocodeFlashRegion(). More detail description is added in UpdateMicrocodeFlashRegion() to improve readability. The Microcode information is collected in InitializeMicrocodeDescriptor(), so that FmpGetImage() can get the info directly. MicrocodeRead() is not needed any more. Cc: Jeff Fan <jeff.fan@intel.com> Cc: Star Zeng <star.zeng@intel.com> Contributed-under: TianoCore Contribution Agreement 1.0 Signed-off-by: Jiewen Yao <jiewen.yao@intel.com> Reviewed-by: Jeff Fan <jeff.fan@intel.com>
* UefiCpuPkg/SmmCpuFeaturesLib: Fix coding style issuesDandan Bi2016-12-213-3/+3
| | | | | | | | Cc: Michael Kinney <michael.d.kinney@intel.com> Cc: Jeff Fan <jeff.fan@intel.com> Contributed-under: TianoCore Contribution Agreement 1.0 Signed-off-by: Dandan Bi <dandan.bi@intel.com> Reviewed-by: Michael Kinney <michael.d.kinney@intel.com>
* UefiCpuPkg: Add Pcd info to uni fileDandan Bi2016-12-211-0/+8
| | | | | | | | | | | Add PcdCpuSmmStmExceptionStackSize/PcdCpuMsegSize prompt and help string to uni file. Cc: Michael Kinney <michael.d.kinney@intel.com> Cc: Jeff Fan <jeff.fan@intel.com> Contributed-under: TianoCore Contribution Agreement 1.0 Signed-off-by: Dandan Bi <dandan.bi@intel.com> Reviewed-by: Michael Kinney <michael.d.kinney@intel.com>
* UefiCpuPkg/PiSmmCpuDxeSmm: Add check to avoid NULL ptr dereferenceHao Wu2016-12-201-0/+8
| | | | | | Contributed-under: TianoCore Contribution Agreement 1.0 Signed-off-by: Hao Wu <hao.a.wu@intel.com> Reviewed-by: Jiewen Yao <jiewen.yao@intel.com>
* UefiCpuPkg/ArchitecturalMsr.h: Remove non-Ascii charactersHao Wu2016-12-201-1/+1
| | | | | | | Contributed-under: TianoCore Contribution Agreement 1.0 Signed-off-by: Hao Wu <hao.a.wu@intel.com> Reviewed-by: Jeff Fan <jeff.fan@intel.com> Reviewed-by: Michael Kinney <michael.d.kinney@intel.com>
* UefiCpuPkg/PiSmmCpu: Add SMM Comm Buffer Paging Protection.Jiewen Yao2016-12-195-12/+324
| | | | | | | | | | | | | | | | | | | | | This patch sets the normal OS buffer EfiLoaderCode/Data, EfiBootServicesCode/Data, EfiConventionalMemory, EfiACPIReclaimMemory to be not present after SmmReadyToLock. To access these region in OS runtime phase is not a good solution. Previously, we did similar check in SmmMemLib to help SMI handler do the check. But if SMI handler forgets the check, it can still access these OS region and bring risk. So here we enforce the policy to prevent it happening. Cc: Jeff Fan <jeff.fan@intel.com> Cc: Michael D Kinney <michael.d.kinney@intel.com> Cc: Laszlo Ersek <lersek@redhat.com> Contributed-under: TianoCore Contribution Agreement 1.0 Signed-off-by: Jiewen Yao <jiewen.yao@intel.com> Reviewed-by: Jeff Fan <jeff.fan@intel.com>
* UefiCpuPkg/SmmCpuFeaturesLibStm: Add STM library instanceMichael Kinney2016-12-1918-0/+4464
| | | | | | | | | | | | | | | | | | | Add a new instances of the SmmCpuFeaturesLib that is used by platforms to enable the SMI Transfer Monitor(STM) feature. This new instance is in the same directory as the default SmmCpuFeaturesLib instance in order to share source files. The DSC file is updated to build both SmmCpuFeatureLib instances and to build two versions of the PiSmmCpuDxeSmm module using each of the SmmCpuFeatureLib instances. Cc: Jiewen Yao <jiewen.yao@intel.com> Cc: Jeff Fan <jeff.fan@intel.com> Cc: Feng Tian <feng.tian@intel.com> Contributed-under: TianoCore Contribution Agreement 1.0 Signed-off-by: Michael Kinney <michael.d.kinney@intel.com> Reviewed-by: Jiewen Yao <jiewen.yao@intel.com> Reviewed-by: Jeff Fan <jeff.fan@intel.com>
* UefiCpuPkg/SmmCpuFeaturesLib: Split into two filesMichael Kinney2016-12-193-62/+107
| | | | | | | | | | | | | | | | | | | | Split the default implementation of the SmmCpuFeaturesLib into two files to prepare for the addition of the STM specific SmmCpuFeaturesLib implementation. The STM specific implementation installs a different SMI entry handler and initialize the MSEG specific MSR at the end of SmmCpuFeaturesInitializeProcessor(). This patch does not introduce any functional changes to the default implementation of the SmmCpuFeaturesLib. Cc: Jiewen Yao <jiewen.yao@intel.com> Cc: Jeff Fan <jeff.fan@intel.com> Cc: Feng Tian <feng.tian@intel.com> Contributed-under: TianoCore Contribution Agreement 1.0 Signed-off-by: Michael Kinney <michael.d.kinney@intel.com> Reviewed-by: Jiewen Yao <jiewen.yao@intel.com> Reviewed-by: Jeff Fan <jeff.fan@intel.com>
* UefiCpuPkg: Add STM GUIDs, Protocols, and PCDsMichael Kinney2016-12-196-0/+1443
| | | | | | | | | | | | | | | | * Add GUIDed HOB that described MSEG region in SMRAM * Add SM Monitor Init Protocol * Add PCD to configure size of SMM exception stack * Add PCD to configure MSEG region size if it is not described by the gMsegSmramGuid GUIDed HOB. Cc: Jiewen Yao <jiewen.yao@intel.com> Cc: Jeff Fan <jeff.fan@intel.com> Cc: Feng Tian <feng.tian@intel.com> Contributed-under: TianoCore Contribution Agreement 1.0 Signed-off-by: Michael Kinney <michael.d.kinney@intel.com> Reviewed-by: Jiewen Yao <jiewen.yao@intel.com> Reviewed-by: Jeff Fan <jeff.fan@intel.com>
* UefiCpuPkg/Include: Update MSEG structure commentsMichael Kinney2016-12-191-3/+22
| | | | | | | | | | | | | Add comments to describe fields of MSEG_HEADER and add define values for the MonitorFeatures field. Cc: Jiewen Yao <jiewen.yao@intel.com> Cc: Jeff Fan <jeff.fan@intel.com> Cc: Feng Tian <feng.tian@intel.com> Contributed-under: TianoCore Contribution Agreement 1.0 Signed-off-by: Michael Kinney <michael.d.kinney@intel.com> Reviewed-by: Jiewen Yao <jiewen.yao@intel.com> Reviewed-by: Jeff Fan <jeff.fan@intel.com>
* UefiCpuPkg/Cpuid.h: Update CPUID definitions with SDM (Sep.2016)Hao Wu2016-12-162-153/+325
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | https://bugzilla.tianocore.org/show_bug.cgi?id=176 Update CPUID leaf and sub-leaf indexes and structures as described by Intel(R) 64 and IA-32 Architectures Software Developer's Manual, Volume 2A, September 2016, CPUID instruction. Summary of incompatible changes: 1. Field name changes in CPUID_STRUCTURED_EXTENDED_FEATURE_FLAGS_EBX Bit 12 has been renamed from 'PQM' to 'RDT_M' and bit 15 has been renamed from 'PQE' to 'RDT_A'. 2. Stucture and filed name changes for 'CPUID Platform QoS Monitoring Information' related definitions Definition 'CPUID_PLATFORM_QOS_MONITORING' has been renamed to 'CPUID_INTEL_RDT_MONITORING'. Definition 'CPUID_PLATFORM_QOS_MONITORING_ENUMERATION_SUB_LEAF' has been renamed to 'CPUID_INTEL_RDT_MONITORING_ENUMERATION_SUB_LEAF'. Definition 'CPUID_PLATFORM_QOS_MONITORING_CAPABILITY_SUB_LEAF' has been renamed to 'CPUID_INTEL_RDT_MONITORING_L3_CACHE_SUB_LEAF'. 3. Stucture and filed name changes for 'CPUID Platform QoS Enforcement Information' related definitions Definition 'CPUID_PLATFORM_QOS_ENFORCEMENT' has been renamed to 'CPUID_INTEL_RDT_ALLOCATION'. Definition 'CPUID_PLATFORM_QOS_ENFORCEMENT_MAIN_LEAF' has been renamed to 'CPUID_INTEL_RDT_ALLOCATION_ENUMERATION_SUB_LEAF'. Definition 'CPUID_PLATFORM_QOS_ENFORCEMENT_RESID_SUB_LEAF' has been renamed to 'CPUID_INTEL_RDT_ALLOCATION_L3_CACHE_SUB_LEAF'. This commit also updates the relating codes in UefiCpuPkg/Application/Cpuid to reflect the changes. Contributed-under: TianoCore Contribution Agreement 1.0 Signed-off-by: Hao Wu <hao.a.wu@intel.com> Reviewed-by: Jeff Fan <jeff.fan@intel.com> Reviewed-by: Michael Kinney <michael.d.kinney@intel.com>
* UefiCpuPkg/Include: Add Goldmont MSR header file with SDM (Sep.2016)Hao Wu2016-12-162-1/+2517
| | | | | | | | | | | | | https://bugzilla.tianocore.org/show_bug.cgi?id=176 Add the MSR header file of Goldmont processor according to Intel(R) 64 and IA-32 Architectures Software Developer's Manual, Volume 3, September 2016, Chapter 35 Model-Specific-Registers (MSR), Section 35.5. Contributed-under: TianoCore Contribution Agreement 1.0 Signed-off-by: Hao Wu <hao.a.wu@intel.com> Reviewed-by: Jeff Fan <jeff.fan@intel.com> Reviewed-by: Michael Kinney <michael.d.kinney@intel.com>
* UefiCpuPkg/Include: Update Skylake MSR header file with SDM (Sep.2016)Hao Wu2016-12-161-20/+1169
| | | | | | | | | | | | | | | | | | https://bugzilla.tianocore.org/show_bug.cgi?id=176 Update the MSR header file of Skylake processor according to Intel(R) 64 and IA-32 Architectures Software Developer's Manual, Volume 3, September 2016, Chapter 35 Model-Specific-Registers (MSR), Section 35.15. Summary of incompatible changes: 1. MSR (address 38EH) IA32_PERF_GLOBAL_STAUS has been renamed to IA32_PERF_GLOBAL_STATUS Typo 'STAUS' has been fixed in SDM. Contributed-under: TianoCore Contribution Agreement 1.0 Signed-off-by: Hao Wu <hao.a.wu@intel.com> Reviewed-by: Jeff Fan <jeff.fan@intel.com> Reviewed-by: Michael Kinney <michael.d.kinney@intel.com>
* UefiCpuPkg/Include: Update MSR header files with SDM (Sep.2016)Hao Wu2016-12-1619-2656/+1312
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | https://bugzilla.tianocore.org/show_bug.cgi?id=176 Update MSR header files of processors (excluding Goldmont and Skylake processors) according to Intel(R) 64 and IA-32 Architectures Software Developer's Manual, Volume 3, September 2016, Chapter 35 Model-Specific-Registers (MSR). Summary of incompatible changes: General: 1. MSR (address 38EH) IA32_PERF_GLOBAL_STAUS in processor-specific header files has been removed or renamed to IA32_PERF_GLOBAL_STATUS Typo 'STAUS' has been fixed in SDM. If the MSR definition is the same with architectural MSR, we remove it. Otherwise, we rename the MSR. 2. MSRs (address starting from 400H) MSR_MC{X}_{XXX} (like MSR_MC4_STATUS) in processor-specific header files have been removed or renamed to IA32_MC{X}_{XXX} (like IA32_MC4_STATUS) Register name change from 'MSR_MC{X}_{XXX}' to 'IA32_MC{X}_{XXX}' in SDM. If the MSR definition is the same with architectural MSR, we remove it. Otherwise, we rename the MSR. Please note that for those MSRs still have name like 'MSR_MC{X}_{XXX}' in SDM are still kept in processor-specific header files. HaswellMsr.h: 1. MSR (address C80H) IA32_DEBUG_FEATURE has been removed Register name change from 'IA32_DEBUG_FEATURE' to 'IA32_DEBUG_INTERFACE' in SDM. Since the MSR definition is the same with architectural MSR, we remove it. SandyBridgeMsr.h: 1. MSR (address 391H) MSR_UNC_PERF_GLOBAL_CTRL, name change for bit fields 0:3 Bit description change from 'Core {X} select' to 'Slice {X} select' for bit 0:3 in SDM. SilvermontMsr.h: 1. MSR (address 2AH) MSR_EBL_CR_POWERON, structure definition changed Bit description for this MSR is totally changed in SDM, we modify the structure definition to align with it. XeonDMsr.h: 1. MSRs (address 630H to 632H) MSR_PKG_C8_RESIDENCY, MSR_PKG_C9_RESIDENCY and MSR_PKG_C10_RESIDENCY have been removed Those 3 MSRs are not defined for this processor in SDM, we remove them. Contributed-under: TianoCore Contribution Agreement 1.0 Signed-off-by: Hao Wu <hao.a.wu@intel.com> Reviewed-by: Jeff Fan <jeff.fan@intel.com> Reviewed-by: Michael Kinney <michael.d.kinney@intel.com>
* UefiCpuPkg/PiSmmCpuDxeSmm: Fix .S & .asm build failureFeng Tian2016-12-164-3/+4
| | | | | | | | | Cc: Michael D Kinney <michael.d.kinney@intel.com> Cc: Jeff Fan <jeff.fan@intel.com> Contributed-under: TianoCore Contribution Agreement 1.0 Signed-off-by: Feng Tian <feng.tian@intel.com> Reviewed-by: Michael D Kinney <michael.d.kinney@intel.com> Reviewed-by: Jeff Fan <jeff.fan@intel.com>
* UefiCpuPkg/Capsule: Fix coding style issuesDandan Bi2016-12-142-0/+2
| | | | | | | | Cc: Jiewen Yao <jiewen.yao@intel.com> Cc: Jeff Fan <jeff.fan@intel.com> Contributed-under: TianoCore Contribution Agreement 1.0 Signed-off-by: Dandan Bi <dandan.bi@intel.com> Reviewed-by: Jiewen Yao <jiewen.yao@intel.com>
* UefiCpuPkg/MicrocodeUpdateDxe: Fix coding style issues in INF fileDandan Bi2016-12-141-2/+3
| | | | | | | | | | | 1. Add MicrocodeUpdate.h to the [Sources] section. 2. Fix the incorrect Guid/Protocol format issues. Cc: Jiewen Yao <jiewen.yao@intel.com> Cc: Jeff Fan <jeff.fan@intel.com> Contributed-under: TianoCore Contribution Agreement 1.0 Signed-off-by: Dandan Bi <dandan.bi@intel.com> Reviewed-by: Jiewen Yao <jiewen.yao@intel.com>
* UefiCpuPkg: Add info string to UNI file for PcdCpuSmmStaticPageTableDandan Bi2016-12-141-0/+8
| | | | | | | | Cc: Jiewen Yao <jiewen.yao@intel.com> Cc: Jeff Fan <jeff.fan@intel.com> Contributed-under: TianoCore Contribution Agreement 1.0 Signed-off-by: Dandan Bi <dandan.bi@intel.com> Reviewed-by: Jiewen Yao <jiewen.yao@intel.com>
* UefiCpuPkg: Make the comments align with the functionsDandan Bi2016-12-148-23/+24
| | | | | | | Cc: Jeff Fan <jeff.fan@intel.com> Contributed-under: TianoCore Contribution Agreement 1.0 Signed-off-by: Dandan Bi <dandan.bi@intel.com> Reviewed-by: Jeff Fan <jeff.fan@intel.com>
* UefiCpuPkg/PiSmmCpuDxeSmm: Remove MTRR field from PSDMichael Kinney2016-12-066-12/+6
| | | | | | | | | | | | | | | | | | | | | https://bugzilla.tianocore.org/show_bug.cgi?id=277 The MTRR field was removed from PROCESS_SMM_DESCRIPTOR structure in commit: https://github.com/tianocore/edk2/commit/26ab5ac3621bdefe96987f8c1512ca79e1bb7ac0 However, the references to the MTRR field in assembly files were not removed. Remove the extern reference to gSmiMtrr and set the Reserved14 field of PROCESS_SMM_DESCRIPTOR to 0. Cc: Jiewen Yao <jiewen.yao@intel.com> Cc: Jeff Fan <jeff.fan@intel.com> Cc: Feng Tian <feng.tian@intel.com> Contributed-under: TianoCore Contribution Agreement 1.0 Signed-off-by: Michael Kinney <michael.d.kinney@intel.com> Reviewed-by: Jeff Fan <jeff.fan@intel.com>
* UefiCpuPkg/PiSmmCpuDxeSmm: Always initialze PSDMichael Kinney2016-12-061-8/+8
| | | | | | | | | | | | | | | | | | | | | | | The following commit moved the initialization of the default PROCESSOR_SMM_DESCRIPTOR from MpService.c to SmramSaveState.c and made this initialization conditional on the value returned by the SmmCpuFeaturesGetSmiHandlerSize() library function. https://github.com/tianocore/edk2/commit/f12367a0b1de7838f1cb8e0839e168ed7b862333 This changed the behavior of the PiSmmCpuDxeSmm module. The initialization of the PROCESSOR_SMM_DESCRIPTOR is moved before the call to SmmCpuFeaturesGetSmiHandlerSize() to preserve the previous behavior. Cc: Jiewen Yao <jiewen.yao@intel.com> Cc: Jeff Fan <jeff.fan@intel.com> Cc: Feng Tian <feng.tian@intel.com> Contributed-under: TianoCore Contribution Agreement 1.0 Signed-off-by: Michael Kinney <michael.d.kinney@intel.com> Reviewed-by: Jeff Fan <jeff.fan@intel.com> Reviewed-by: Feng Tian <feng.tian@intel.com>
* UefiCpuPkg/PiSmmCpu: Fixed #double fault on #page fault.Jiewen Yao2016-12-074-49/+171
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | This patch fixes https://bugzilla.tianocore.org/show_bug.cgi?id=246 Previously, when SMM exception happens after EndOfDxe, with StackGuard enabled on IA32, the #double fault exception is reported instead of #page fault. Root cause is below: Current EDKII SMM page protection will lock GDT. If IA32 stack guard is enabled, the page fault handler will do task switch. This task switch need write busy flag in GDT, and write TSS. However, the GDT and TSS is locked at that time, so the double fault happens. We decide to not lock GDT for IA32 StackGuard enabled. This issue does not exist on X64, or IA32 without StackGuard. Cc: Laszlo Ersek <lersek@redhat.com> Cc: Jeff Fan <jeff.fan@intel.com> Cc: Michael D Kinney <michael.d.kinney@intel.com> Contributed-under: TianoCore Contribution Agreement 1.0 Signed-off-by: Jiewen Yao <jiewen.yao@intel.com> Reviewed-by: Jeff Fan <jeff.fan@intel.com> Regression-tested-by: Laszlo Ersek <lersek@redhat.com>
* UefiCpuPkg/Include: Add VMX MSR register structuresMichael Kinney2016-12-011-5/+219
| | | | | | | | | | | | | | | | https://bugzilla.tianocore.org/show_bug.cgi?id=279 Add MSR_IA32_VMX_BASIC_REGISTER and IA32_VMX_MISC_REGISTER structures with the bit fields for these two MSRs. Also add MSEG_HEADER structure whose base address is in the MsegBase field of MSR_IA32_SMM_MONITOR_CTL_REGISTER. Cc: Jiewen Yao <jiewen.yao@intel.com> Cc: Jeff Fan <jeff.fan@intel.com> Cc: Feng Tian <feng.tian@intel.com> Contributed-under: TianoCore Contribution Agreement 1.0 Signed-off-by: Michael Kinney <michael.d.kinney@intel.com> Reviewed-by: Jeff Fan <jeff.fan@intel.com>
* UefiCpuPkg/PiSmmCpuDxeSmm: Remove PSD layout assumptionsMichael Kinney2016-12-018-47/+60
| | | | | | | | | | | | | | | | | | | https://bugzilla.tianocore.org/show_bug.cgi?id=277 Remove dependency on layout of PROCESSOR_SMM_DESCRIPTOR everywhere possible. The only exception is the standard SMI entry handler template that is included with the PiSmmCpuDxeSmm module. This allows an instance of the SmmCpuFeaturesLib to provide alternate PROCESSOR_SMM_DESCRIPTOR structure layouts. Cc: Jiewen Yao <jiewen.yao@intel.com> Cc: Jeff Fan <jeff.fan@intel.com> Cc: Feng Tian <feng.tian@intel.com> Contributed-under: TianoCore Contribution Agreement 1.0 Signed-off-by: Michael Kinney <michael.d.kinney@intel.com> Reviewed-by: Jeff Fan <jeff.fan@intel.com> Reviewed-by: Feng Tian <feng.tian@intel.com>
* UefiCpuPkg/PiSmmCpuDxeSmm: Remove MTRRs from PSD structureMichael Kinney2016-12-012-15/+5
| | | | | | | | | | | | | | | | https://bugzilla.tianocore.org/show_bug.cgi?id=277 All CPUs use the same MTRR settings. Move MTRR settings from a field in the PROCESSOR_SMM_DESCRIPTOR structure into a module global variable. Cc: Jiewen Yao <jiewen.yao@intel.com> Cc: Jeff Fan <jeff.fan@intel.com> Cc: Feng Tian <feng.tian@intel.com> Contributed-under: TianoCore Contribution Agreement 1.0 Signed-off-by: Michael Kinney <michael.d.kinney@intel.com> Reviewed-by: Jeff Fan <jeff.fan@intel.com> Reviewed-by: Feng Tian <feng.tian@intel.com>
* UefiCpuPkg/CpuExceptionHandlerLib: remove un-used mReservedVectorsJeff Fan2016-12-012-4/+2
| | | | | | | | | Cc: Feng Tian <feng.tian@intel.com> Cc: Jiewen Yao <jiewen.yao@intel.com> Cc: Michael D Kinney <michael.d.kinney@intel.com> Contributed-under: TianoCore Contribution Agreement 1.0 Signed-off-by: Jeff Fan <jeff.fan@intel.com> Reviewed-by: Feng Tian <feng.tian@intel.com>
* UefiCpuPkg: Add ExceptionHandlerData for ArchRestoreExceptionContext()Jeff Fan2016-12-014-24/+35
| | | | | | | | | | | | mReservedVectors is not set, we could add parameter ExceptionHandlerData for ArchRestoreExceptionContext() that could use it instead of mReservedVectors. Cc: Feng Tian <feng.tian@intel.com> Cc: Jiewen Yao <jiewen.yao@intel.com> Cc: Michael D Kinney <michael.d.kinney@intel.com> Contributed-under: TianoCore Contribution Agreement 1.0 Signed-off-by: Jeff Fan <jeff.fan@intel.com> Reviewed-by: Feng Tian <feng.tian@intel.com>
* UefiCpuPkg: Add ExceptionHandlerData for ArchSaveExceptionContext()Jeff Fan2016-12-014-29/+39
| | | | | | | | | | | | mReservedVectors is not set, we could add parameter ExceptionHandlerData for ArchSaveExceptionContext() that could use it instead of mReservedVectors. Cc: Feng Tian <feng.tian@intel.com> Cc: Jiewen Yao <jiewen.yao@intel.com> Cc: Michael D Kinney <michael.d.kinney@intel.com> Contributed-under: TianoCore Contribution Agreement 1.0 Signed-off-by: Jeff Fan <jeff.fan@intel.com> Reviewed-by: Feng Tian <feng.tian@intel.com>
* UefiCpuPkg/PiSmmCpuDxeSmm: Clear some semaphores on S3 boot pathJeff Fan2016-12-011-0/+3
| | | | | | | | | | | | | | | | | | | | | | Some semaphores are not cleared on S3 boot path. For example, mSmmMpSyncData->CpuData[CpuIndex].Present. It may still keeps the value set at SMM runtime during S3 resume. It may causes BSP have the wrong judgement on SMM AP's present state. We have one related fix at e78a2a49ee6b0c0d7c6997c87ace31d7761cf636. But that is not completed. This fix is to clear Busy/Run/Present semaphores in InitializeMpSyncData(). Cc: Laszlo Ersek <lersek@redhat.com> Cc: Feng Tian <feng.tian@intel.com> Cc: Jiewen Yao <jiewen.yao@intel.com> Cc: Michael D Kinney <michael.d.kinney@intel.com> Contributed-under: TianoCore Contribution Agreement 1.0 Signed-off-by: Jeff Fan <jeff.fan@intel.com> Acked-by: Laszlo Ersek <lersek@redhat.com> Tested-by: Laszlo Ersek <lersek@redhat.com> Reviewed-by: Feng Tian <feng.tian@intel.com>
* UefiCpuPkg/MicrocodeUpdate: Fix GetImage APIJiewen Yao2016-11-301-0/+10
| | | | | | | | | | | Current GetImage API forgets to return data to caller. Add code to fix it. Cc: Jeff Fan <jeff.fan@intel.com> Contributed-under: TianoCore Contribution Agreement 1.0 Signed-off-by: Jiewen Yao <jiewen.yao@intel.com> Reviewed-by: Jeff Fan <jeff.fan@intel.com>
generated by cgit v1.2.3 (git 2.25.1) at 2024-06-27 09:08:34 +0000