blob: 7368ce7af02acda4bfa975b46e39e8f1bd3f2b62 (
plain)
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50
51
52
53
54
55
56
57
58
59
60
61
62
63
64
65
66
67
68
69
70
71
72
73
74
75
76
77
78
79
80
81
82
83
84
85
86
87
88
89
90
91
92
93
94
95
96
97
98
99
100
101
102
103
104
105
106
107
|
/** @file
MSR Definitions.
Provides defines for Machine Specific Registers(MSR) indexes. Data structures
are provided for MSRs that contain one or more bit fields. If the MSR value
returned is a single 32-bit or 64-bit value, then a data structure is not
provided for that MSR.
Copyright (c) 2017, Advanced Micro Devices. All rights reserved.<BR>
SPDX-License-Identifier: BSD-2-Clause-Patent
@par Specification Reference:
AMD64 Architecture Programming Manual volume 2, March 2017, Sections 15.34
**/
#ifndef __FAM17_MSR_H__
#define __FAM17_MSR_H__
/**
Secure Encrypted Virtualization - Encrypted State (SEV-ES) GHCB register
**/
#define MSR_SEV_ES_GHCB 0xc0010130
/**
MSR information returned for #MSR_SEV_ES_GHCB
**/
typedef union {
struct {
UINT32 Function:12;
UINT32 Reserved1:20;
UINT32 Reserved2:32;
} GhcbInfo;
struct {
UINT8 Reserved[3];
UINT8 SevEncryptionBitPos;
UINT16 SevEsProtocolMin;
UINT16 SevEsProtocolMax;
} GhcbProtocol;
struct {
UINT32 Function:12;
UINT32 ReasonCodeSet:4;
UINT32 ReasonCode:8;
UINT32 Reserved1:8;
UINT32 Reserved2:32;
} GhcbTerminate;
VOID *Ghcb;
UINT64 GhcbPhysicalAddress;
} MSR_SEV_ES_GHCB_REGISTER;
#define GHCB_INFO_SEV_INFO 1
#define GHCB_INFO_SEV_INFO_GET 2
#define GHCB_INFO_CPUID_REQUEST 4
#define GHCB_INFO_CPUID_RESPONSE 5
#define GHCB_INFO_TERMINATE_REQUEST 256
#define GHCB_TERMINATE_GHCB 0
#define GHCB_TERMINATE_GHCB_GENERAL 0
#define GHCB_TERMINATE_GHCB_PROTOCOL 1
/**
Secure Encrypted Virtualization (SEV) status register
**/
#define MSR_SEV_STATUS 0xc0010131
/**
MSR information returned for #MSR_SEV_STATUS
**/
typedef union {
///
/// Individual bit fields
///
struct {
///
/// [Bit 0] Secure Encrypted Virtualization (Sev) is enabled
///
UINT32 SevBit:1;
///
/// [Bit 1] Secure Encrypted Virtualization Encrypted State (SevEs) is enabled
///
UINT32 SevEsBit:1;
///
/// [Bit 2] Secure Nested Paging (SevSnp) is enabled
///
UINT32 SevSnpBit:1;
UINT32 Reserved2:29;
} Bits;
///
/// All bit fields as a 32-bit value
///
UINT32 Uint32;
///
/// All bit fields as a 64-bit value
///
UINT64 Uint64;
} MSR_SEV_STATUS_REGISTER;
#endif
|
