blob: ac8f92f38aed1c22f563f3fd0f4a6a77f0d1b87a (
plain)
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
|
//------------------------------------------------------------------------------
//
// CPU scratch register related functions for RISC-V
//
// Copyright (c) 2020, Hewlett Packard Enterprise Development LP. All rights reserved.<BR>
//
// SPDX-License-Identifier: BSD-2-Clause-Patent
//
//------------------------------------------------------------------------------
#include <Register/RiscV64/RiscVImpl.h>
.data
.align 3
.section .text
//
// Set Supervisor Address Translation and
// Protection Register.
//
ASM_FUNC (RiscVSetSupervisorAddressTranslationRegister)
csrw CSR_SATP, a0
ret
|
