1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50
51
52
53
54
55
56
57
58
59
60
61
62
63
64
65
66
67
68
69
70
71
72
73
74
75
76
77
78
79
80
81
82
83
84
85
86
87
88
89
90
91
92
93
94
95
96
97
98
99
100
101
102
103
104
105
106
107
108
109
110
111
112
113
114
115
116
117
118
119
120
121
122
123
124
125
126
127
128
129
130
131
132
133
134
135
136
137
138
139
140
141
142
143
144
145
146
147
148
149
150
151
152
153
154
155
156
157
158
159
160
161
162
163
164
165
166
167
168
169
170
171
172
173
174
175
176
177
178
179
180
181
182
183
184
185
186
187
188
189
190
191
192
193
194
195
196
197
198
199
200
201
202
203
204
205
206
207
208
209
210
211
212
213
214
215
216
217
218
219
220
221
222
223
224
225
|
/** @file
Framework PEIM to initialize memory on an DDR2 SDRAM Memory Controller.
Copyright (c) 2013 - 2016 Intel Corporation.
SPDX-License-Identifier: BSD-2-Clause-Patent
**/
#ifndef _MRC_WRAPPER_H
#define _MRC_WRAPPER_H
#include <Ppi/QNCMemoryInit.h>
#include "PlatformEarlyInit.h"
//
// Define the default memory areas required
//
#define EDKII_RESERVED_SIZE_PAGES 0x20
#define ACPI_NVS_SIZE_PAGES 0x60
#define RUNTIME_SERVICES_DATA_SIZE_PAGES 0x20
#define RUNTIME_SERVICES_CODE_SIZE_PAGES 0x80
#define ACPI_RECLAIM_SIZE_PAGES 0x20
#define EDKII_DXE_MEM_SIZE_PAGES 0x20
//
// Maximum number of "Socket Sets", where a "Socket Set is a set of matching
// DIMM's from the various channels
//
#define MAX_SOCKET_SETS 2
//
// Maximum number of memory ranges supported by the memory controller
//
#define MAX_RANGES (MAX_ROWS + 5)
//
// Min. of 48MB PEI phase
//
#define PEI_MIN_MEMORY_SIZE (6 * 0x800000)
#define PEI_RECOVERY_MIN_MEMORY_SIZE (6 * 0x800000)
#define PEI_MEMORY_RANGE_OPTION_ROM UINT32
#define PEI_MR_OPTION_ROM_NONE 0x00000000
//
// SMRAM Memory Range
//
#define PEI_MEMORY_RANGE_SMRAM UINT32
#define PEI_MR_SMRAM_ALL 0xFFFFFFFF
#define PEI_MR_SMRAM_NONE 0x00000000
#define PEI_MR_SMRAM_CACHEABLE_MASK 0x80000000
#define PEI_MR_SMRAM_SEGTYPE_MASK 0x00FF0000
#define PEI_MR_SMRAM_ABSEG_MASK 0x00010000
#define PEI_MR_SMRAM_HSEG_MASK 0x00020000
#define PEI_MR_SMRAM_TSEG_MASK 0x00040000
//
// SMRAM Size is a multiple of 128KB.
//
#define PEI_MR_SMRAM_SIZE_MASK 0x0000FFFF
//
// Pci Memory Hole
//
#define PEI_MEMORY_RANGE_PCI_MEMORY UINT32
typedef enum {
Ignore,
Quick,
Sparse,
Extensive
} PEI_MEMORY_TEST_OP;
//
// MRC Params Variable structure.
//
typedef struct {
MrcTimings_t timings; // Actual MRC config values saved in variable store.
UINT8 VariableStorePad[8]; // Allow for data stored in variable is required to be multiple of 8bytes.
} PLATFORM_VARIABLE_MEMORY_CONFIG_DATA;
///
/// MRC Params Platform Data Flags bits
///
#define PDAT_MRC_FLAG_ECC_EN BIT0
#define PDAT_MRC_FLAG_SCRAMBLE_EN BIT1
#define PDAT_MRC_FLAG_MEMTEST_EN BIT2
#define PDAT_MRC_FLAG_TOP_TREE_EN BIT3 ///< 0b DDR "fly-by" topology else 1b DDR "tree" topology.
#define PDAT_MRC_FLAG_WR_ODT_EN BIT4 ///< If set ODR signal is asserted to DRAM devices on writes.
///
/// MRC Params Platform Data.
///
typedef struct {
UINT32 Flags; ///< Bitmap of PDAT_MRC_FLAG_XXX defs above.
UINT8 DramWidth; ///< 0=x8, 1=x16, others=RESERVED.
UINT8 DramSpeed; ///< 0=DDRFREQ_800, 1=DDRFREQ_1066, others=RESERVED. Only 533MHz SKU support 1066 memory.
UINT8 DramType; ///< 0=DDR3,1=DDR3L, others=RESERVED.
UINT8 RankMask; ///< bit[0] RANK0_EN, bit[1] RANK1_EN, others=RESERVED.
UINT8 ChanMask; ///< bit[0] CHAN0_EN, others=RESERVED.
UINT8 ChanWidth; ///< 1=x16, others=RESERVED.
UINT8 AddrMode; ///< 0, 1, 2 (mode 2 forced if ecc enabled), others=RESERVED.
UINT8 SrInt; ///< 1=1.95us, 2=3.9us, 3=7.8us, others=RESERVED. REFRESH_RATE.
UINT8 SrTemp; ///< 0=normal, 1=extended, others=RESERVED.
UINT8 DramRonVal; ///< 0=34ohm, 1=40ohm, others=RESERVED. RON_VALUE Select MRS1.DIC driver impedance control.
UINT8 DramRttNomVal; ///< 0=40ohm, 1=60ohm, 2=120ohm, others=RESERVED.
UINT8 DramRttWrVal; ///< 0=off others=RESERVED.
UINT8 SocRdOdtVal; ///< 0=off, 1=60ohm, 2=120ohm, 3=180ohm, others=RESERVED.
UINT8 SocWrRonVal; ///< 0=27ohm, 1=32ohm, 2=40ohm, others=RESERVED.
UINT8 SocWrSlewRate; ///< 0=2.5V/ns, 1=4V/ns, others=RESERVED.
UINT8 DramDensity; ///< 0=512Mb, 1=1Gb, 2=2Gb, 3=4Gb, others=RESERVED.
UINT32 tRAS; ///< ACT to PRE command period in picoseconds.
UINT32 tWTR; ///< Delay from start of internal write transaction to internal read command in picoseconds.
UINT32 tRRD; ///< ACT to ACT command period (JESD79 specific to page size 1K/2K) in picoseconds.
UINT32 tFAW; ///< Four activate window (JESD79 specific to page size 1K/2K) in picoseconds.
UINT8 tCL; ///< DRAM CAS Latency in clocks.
} PDAT_MRC_ITEM;
//
// Memory range types
//
typedef enum {
DualChannelDdrMainMemory,
DualChannelDdrSmramCacheable,
DualChannelDdrSmramNonCacheable,
DualChannelDdrGraphicsMemoryCacheable,
DualChannelDdrGraphicsMemoryNonCacheable,
DualChannelDdrReservedMemory,
DualChannelDdrMaxMemoryRangeType
} PEI_DUAL_CHANNEL_DDR_MEMORY_RANGE_TYPE;
//
// Memory map range information
//
typedef struct {
EFI_PHYSICAL_ADDRESS PhysicalAddress;
EFI_PHYSICAL_ADDRESS CpuAddress;
EFI_PHYSICAL_ADDRESS RangeLength;
PEI_DUAL_CHANNEL_DDR_MEMORY_RANGE_TYPE Type;
} PEI_DUAL_CHANNEL_DDR_MEMORY_MAP_RANGE;
//
// Function prototypes.
//
EFI_STATUS
InstallEfiMemory (
IN EFI_PEI_SERVICES **PeiServices,
IN EFI_PEI_READ_ONLY_VARIABLE2_PPI *VariableServices,
IN EFI_BOOT_MODE BootMode,
IN UINT32 TotalMemorySize
);
EFI_STATUS
InstallS3Memory (
IN EFI_PEI_SERVICES **PeiServices,
IN EFI_PEI_READ_ONLY_VARIABLE2_PPI *VariableServices,
IN UINT32 TotalMemorySize
);
EFI_STATUS
MemoryInit (
IN EFI_PEI_SERVICES **PeiServices
);
EFI_STATUS
LoadConfig (
IN EFI_PEI_SERVICES **PeiServices,
IN EFI_PEI_READ_ONLY_VARIABLE2_PPI *VariableServices,
IN OUT MRCParams_t *MrcData
);
EFI_STATUS
SaveConfig (
IN MRCParams_t *MrcData
);
EFI_STATUS
GetMemoryMap (
IN EFI_PEI_SERVICES **PeiServices,
IN UINT32 TotalMemorySize,
IN OUT PEI_DUAL_CHANNEL_DDR_MEMORY_MAP_RANGE *MemoryMap,
IN OUT UINT8 *NumRanges
);
EFI_STATUS
ChooseRanges (
IN OUT PEI_MEMORY_RANGE_OPTION_ROM *OptionRomMask,
IN OUT PEI_MEMORY_RANGE_SMRAM *SmramMask,
IN OUT PEI_MEMORY_RANGE_PCI_MEMORY *PciMemoryMask
);
EFI_STATUS
GetPlatformMemorySize (
IN EFI_PEI_SERVICES **PeiServices,
IN EFI_BOOT_MODE BootMode,
IN OUT UINT64 *MemorySize
);
EFI_STATUS
BaseMemoryTest (
IN EFI_PEI_SERVICES **PeiServices,
IN EFI_PHYSICAL_ADDRESS BeginAddress,
IN UINT64 MemoryLength,
IN PEI_MEMORY_TEST_OP Operation,
OUT EFI_PHYSICAL_ADDRESS *ErrorAddress
);
EFI_STATUS
SetPlatformImrPolicy (
IN EFI_PHYSICAL_ADDRESS PeiMemoryBaseAddress,
IN UINT64 PeiMemoryLength
);
VOID
EFIAPI
InfoPostInstallMemory (
OUT UINT32 *RmuBaseAddressPtr OPTIONAL,
OUT EFI_SMRAM_DESCRIPTOR **SmramDescriptorPtr OPTIONAL,
OUT UINTN *NumSmramRegionsPtr OPTIONAL
);
#endif
|
