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| author | Edward O'Callaghan <quasisec@google.com> | 2020-10-15 19:19:05 +1100 |
|---|---|---|
| committer | Felix Singer <felixsinger@posteo.net> | 2022-09-29 17:05:15 +0000 |
| commit | eaf701dc68e1b6a38542c3c856b0c9a2fb5a826d (patch) | |
| tree | 5541efefb64efc6611a315e12936608c37803c3c | |
| parent | d92dd50bcac6b2d0dfffa9f983712f7400990f3d (diff) | |
| download | flashrom-eaf701dc68e1b6a38542c3c856b0c9a2fb5a826d.tar.gz flashrom-eaf701dc68e1b6a38542c3c856b0c9a2fb5a826d.tar.bz2 flashrom-eaf701dc68e1b6a38542c3c856b0c9a2fb5a826d.zip | |
chipset_enable.c: check return value from rphysmap() call
Port from the ChromiumOS fork of flashrom.
Change-Id: I8075fe5f80ac0da5280d2f0de6829ed3a2496476
Signed-off-by: Edward O'Callaghan <quasisec@google.com>
Reviewed-on: https://review.coreboot.org/c/flashrom/+/46444
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Sam McNally <sammc@google.com>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/c/flashrom/+/67867
Reviewed-by: Felix Singer <felixsinger@posteo.net>
| -rw-r--r-- | chipset_enable.c | 2 |
1 files changed, 2 insertions, 0 deletions
diff --git a/chipset_enable.c b/chipset_enable.c index 0dfe26756..5195b9503 100644 --- a/chipset_enable.c +++ b/chipset_enable.c @@ -1002,6 +1002,8 @@ static int enable_flash_silvermont(struct pci_dev *dev, const char *name) uint32_t sbase = pci_read_long(dev, 0x54) & 0xfffffe00; msg_pdbg("SPI_BASE_ADDRESS = 0x%x\n", sbase); void *spibar = rphysmap("BYT SBASE", sbase, 512); /* Last defined address on Bay Trail is 0x100 */ + if (spibar == ERROR_PTR) + return ERROR_FATAL; /* Enable Flash Writes. * Silvermont-based: BCR at SBASE + 0xFC (some bits of BCR are also accessible via BC at IBASE + 0x1C). |