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authorNico Huber <nico.huber@secunet.com>2017-03-17 17:22:53 +0100
committerNico Huber <nico.h@gmx.de>2017-04-25 18:53:50 +0200
commit0ea99f57c9d8fe28600cd08f653c10e5c0c0dd3f (patch)
treedda8ea443bd14845e927838fa2e27fba61761584
parentb4d8a2a64b72d65e447161179279c108709c0ac3 (diff)
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Move register decodes into enable_flash_ich_handle_gcs()
GCS was decoded partly inside, partly outside this function. The decoding of `top_swap` was off, since passing a `uint8_t` as `bool` doesn't magically check bit0 only. While we are at it, rename this void function to enable_flash_ich_ report_gcs() as it's not doing anything. Beside debug output it doesn't have any side effects. Change-Id: I40addec98cb6840763adad30f9d0e27dadce6d1e Signed-off-by: Nico Huber <nico.huber@secunet.com> Reviewed-on: https://review.coreboot.org/18882 Tested-by: build bot (Jenkins) Reviewed-by: Philippe Mathieu-Daudé <philippe.mathieu.daude@gmail.com> Reviewed-by: Arthur Heymans <arthur@aheymans.xyz> Reviewed-by: Youness Alaoui <snifikino@gmail.com>
-rw-r--r--chipset_enable.c22
1 files changed, 18 insertions, 4 deletions
diff --git a/chipset_enable.c b/chipset_enable.c
index b181b9349..1191a4c10 100644
--- a/chipset_enable.c
+++ b/chipset_enable.c
@@ -584,8 +584,23 @@ static int enable_flash_poulsbo(struct pci_dev *dev, const char *name)
return enable_flash_ich_fwh(dev, CHIPSET_POULSBO, 0xd8);
}
-static void enable_flash_ich_handle_gcs(struct pci_dev *dev, enum ich_chipset ich_generation, uint32_t gcs, bool top_swap)
+static void enable_flash_ich_report_gcs(struct pci_dev *const dev, const enum ich_chipset ich_generation,
+ const uint8_t *const rcrb)
{
+ uint32_t gcs;
+ bool top_swap;
+
+ switch (ich_generation) {
+ case CHIPSET_BAYTRAIL:
+ gcs = mmio_readl(rcrb + 0);
+ top_swap = (gcs & 2) >> 1;
+ break;
+ default:
+ gcs = mmio_readl(rcrb + 0x3410);
+ top_swap = mmio_readb(rcrb + 0x3414) & 1;
+ break;
+ }
+
msg_pdbg("GCS = 0x%x: ", gcs);
msg_pdbg("BIOS Interface Lock-Down: %sabled, ", (gcs & 0x1) ? "en" : "dis");
@@ -673,7 +688,7 @@ static int enable_flash_ich_spi(struct pci_dev *dev, enum ich_chipset ich_genera
if (rcrb == ERROR_PTR)
return ERROR_FATAL;
- enable_flash_ich_handle_gcs(dev, ich_generation, mmio_readl(rcrb + 0x3410), mmio_readb(rcrb + 0x3414));
+ enable_flash_ich_report_gcs(dev, ich_generation, rcrb);
/* Handle FWH-related parameters and initialization */
int ret_fwh = enable_flash_ich_fwh(dev, ich_generation, bios_cntl);
@@ -803,8 +818,7 @@ static int enable_flash_silvermont(struct pci_dev *dev, const char *name)
/* Handle GCS (in RCRB) */
void *rcrb = physmap("BYT RCRB", rcba, 4);
- uint32_t gcs = mmio_readl(rcrb + 0);
- enable_flash_ich_handle_gcs(dev, ich_generation, gcs, gcs & 0x2);
+ enable_flash_ich_report_gcs(dev, ich_generation, rcrb);
physunmap(rcrb, 4);
/* Handle fwh_idsel parameter */