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| author | Carl-Daniel Hailfinger <c-d.hailfinger.devel.2006@gmx.net> | 2009-05-26 21:25:08 +0000 |
|---|---|---|
| committer | Carl-Daniel Hailfinger <c-d.hailfinger.devel.2006@gmx.net> | 2009-05-26 21:25:08 +0000 |
| commit | 15aa7c65430312c14df2854f6086c5e44de9a79d (patch) | |
| tree | 1f802b306afb2a7ab4f1009da21ac202488fda25 | |
| parent | 90e8e613183a817553511f670852100a42fe39be (diff) | |
| download | flashrom-15aa7c65430312c14df2854f6086c5e44de9a79d.tar.gz flashrom-15aa7c65430312c14df2854f6086c5e44de9a79d.tar.bz2 flashrom-15aa7c65430312c14df2854f6086c5e44de9a79d.zip | |
Use REMS instead of RES in the ICH SPI default opcode table
RES is Read Electronic Signature (1 Byte, identical for different chips)
REMS is Read Electronic Manufacturer Signature (2 Bytes, mostly unique)
RDID is Read JEDEC ID (3 bytes, unique)
Of the chips which don't support RDID, a sizable portion supports REMS
which gives us both a manufacturer ID and a device ID. This is clearly
superior to having only a device ID (the RES case) which has multiple
documented collisions.
The RES/REMS problem is aggravated by inconsistent naming in vendor data
sheets. What's in a name? Considering that we have 1-byte IDs, 2-byte
IDs and 3+byte IDs with varying names but mostly consistent opcodes, it
makes sense to set our own standard about how the opcodes are called.
The best way forward would be to have the ICH SPI driver reprogram the
opcode menu on the fly if the opcode menu doesn't contain the requested
opcode and the opcode menu is not locked. Until that happens, this patch
improves detection accuracy by a factor of 256 for some chips.
Corresponding to flashrom svn r549.
Signed-off-by: Carl-Daniel Hailfinger <c-d.hailfinger.devel.2006@gmx.net>
Tested-by: Uwe Hermann
with the flash chip "SST SST25VF040.REMS".
Acked-by: Ronald G. Minnich <rminnich@gmail.com>
| -rw-r--r-- | ichspi.c | 2 |
1 files changed, 1 insertions, 1 deletions
@@ -179,7 +179,7 @@ OPCODES O_ST_M25P = { {JEDEC_READ, SPI_OPCODE_TYPE_READ_WITH_ADDRESS, 0}, // Read Data {JEDEC_BE_D8, SPI_OPCODE_TYPE_WRITE_WITH_ADDRESS, 1}, // Erase Sector {JEDEC_RDSR, SPI_OPCODE_TYPE_READ_NO_ADDRESS, 0}, // Read Device Status Reg - {JEDEC_RES, SPI_OPCODE_TYPE_READ_WITH_ADDRESS, 0}, // Resume Deep Power-Down + {JEDEC_REMS, SPI_OPCODE_TYPE_READ_WITH_ADDRESS, 0}, // Read Electronic Manufacturer Signature {JEDEC_WRSR, SPI_OPCODE_TYPE_WRITE_NO_ADDRESS, 1}, // Write Status Register {JEDEC_RDID, SPI_OPCODE_TYPE_READ_NO_ADDRESS, 0}, // Read JDEC ID {JEDEC_CE_C7, SPI_OPCODE_TYPE_WRITE_NO_ADDRESS, 1}, // Bulk erase |