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author | Alexander Goncharov <chat@joursoir.net> | 2022-07-13 13:54:44 +0300 |
---|---|---|
committer | Anastasia Klimchuk <aklm@chromium.org> | 2022-08-05 09:00:58 +0000 |
commit | 65372382c3933fca0c31cdf32e17f9d171af8840 (patch) | |
tree | 34b97e0c8b5e30f20e182f03eb8d28c2d123c81e | |
parent | e410532fdd45855a2aaac028d8129204346259d8 (diff) | |
download | flashrom-65372382c3933fca0c31cdf32e17f9d171af8840.tar.gz flashrom-65372382c3933fca0c31cdf32e17f9d171af8840.tar.bz2 flashrom-65372382c3933fca0c31cdf32e17f9d171af8840.zip |
satamv: Refactor singleton states into reentrant pattern
Move global singleton states into a struct and store within
the par_master data field for the life-time of the driver.
This is one of the steps on the way to move par_master data
memory management behind the initialisation API, for more
context see other patches under the same topic specified below.
TOPIC=register_master_api
TEST=builds
Change-Id: I084cf826a8a594ade80eed43008e286c7bd1b553
Signed-off-by: Alexander Goncharov <chat@joursoir.net>
Ticket: https://ticket.coreboot.org/issues/391
Reviewed-on: https://review.coreboot.org/c/flashrom/+/65978
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Thomas Heijligen <src@posteo.de>
Reviewed-by: Anastasia Klimchuk <aklm@chromium.org>
Reviewed-by: Felix Singer <felixsinger@posteo.net>
-rw-r--r-- | satamv.c | 65 |
1 files changed, 44 insertions, 21 deletions
@@ -23,8 +23,10 @@ #include "hwaccess_physmap.h" #include "platform/pci.h" -static uint8_t *mv_bar; -static uint16_t mv_iobar; +struct satamv_data { + uint8_t *mv_bar; + uint16_t mv_iobar; +}; static const struct dev_entry satas_mv[] = { /* 88SX6041 and 88SX6042 are the same according to the datasheet. */ @@ -45,33 +47,43 @@ static const struct dev_entry satas_mv[] = { */ /* Indirect access to via the I/O BAR1. */ -static void satamv_indirect_chip_writeb(uint8_t val, chipaddr addr) +static void satamv_indirect_chip_writeb(uint8_t val, chipaddr addr, uint16_t iobar) { /* 0x80000000 selects BAR2 for remapping. */ - OUTL(((uint32_t)addr | 0x80000000) & 0xfffffffc, mv_iobar); - OUTB(val, mv_iobar + 0x80 + (addr & 0x3)); + OUTL(((uint32_t)addr | 0x80000000) & 0xfffffffc, iobar); + OUTB(val, iobar + 0x80 + (addr & 0x3)); } /* Indirect access to via the I/O BAR1. */ -static uint8_t satamv_indirect_chip_readb(const chipaddr addr) +static uint8_t satamv_indirect_chip_readb(const chipaddr addr, uint16_t iobar) { /* 0x80000000 selects BAR2 for remapping. */ - OUTL(((uint32_t)addr | 0x80000000) & 0xfffffffc, mv_iobar); - return INB(mv_iobar + 0x80 + (addr & 0x3)); + OUTL(((uint32_t)addr | 0x80000000) & 0xfffffffc, iobar); + return INB(iobar + 0x80 + (addr & 0x3)); } /* FIXME: Prefer direct access to BAR2 if BAR2 is active. */ static void satamv_chip_writeb(const struct flashctx *flash, uint8_t val, chipaddr addr) { - satamv_indirect_chip_writeb(val, addr); + const struct satamv_data *data = flash->mst->par.data; + + satamv_indirect_chip_writeb(val, addr, data->mv_iobar); } /* FIXME: Prefer direct access to BAR2 if BAR2 is active. */ static uint8_t satamv_chip_readb(const struct flashctx *flash, const chipaddr addr) { - return satamv_indirect_chip_readb(addr); + const struct satamv_data *data = flash->mst->par.data; + + return satamv_indirect_chip_readb(addr, data->mv_iobar); +} + +static int satamv_shutdown(void *par_data) +{ + free(par_data); + return 0; } static const struct par_master par_master_satamv = { @@ -83,6 +95,7 @@ static const struct par_master par_master_satamv = { .chip_writew = fallback_chip_writew, .chip_writel = fallback_chip_writel, .chip_writen = fallback_chip_writen, + .shutdown = satamv_shutdown, }; /* @@ -106,6 +119,8 @@ static int satamv_init(void) struct pci_dev *dev = NULL; uintptr_t addr; uint32_t tmp; + uint16_t iobar; + uint8_t *bar; if (rget_io_perms()) return 1; @@ -119,11 +134,11 @@ static int satamv_init(void) if (!addr) return 1; - mv_bar = rphysmap("Marvell 88SX7042 registers", addr, 0x20000); - if (mv_bar == ERROR_PTR) + bar = rphysmap("Marvell 88SX7042 registers", addr, 0x20000); + if (bar == ERROR_PTR) return 1; - tmp = pci_mmio_readl(mv_bar + FLASH_PARAM); + tmp = pci_mmio_readl(bar + FLASH_PARAM); msg_pspew("Flash Parameters:\n"); msg_pspew("TurnOff=0x%01x\n", (tmp >> 0) & 0x7); msg_pspew("Acc2First=0x%01x\n", (tmp >> 3) & 0xf); @@ -140,22 +155,22 @@ static int satamv_init(void) msg_pspew("WrHighExt=0x%01x\n", (tmp >> 27) & 0x1); msg_pspew("Reserved[31:28]=0x%01x\n", (tmp >> 28) & 0xf); - tmp = pci_mmio_readl(mv_bar + EXPANSION_ROM_BAR_CONTROL); + tmp = pci_mmio_readl(bar + EXPANSION_ROM_BAR_CONTROL); msg_pspew("Expansion ROM BAR Control:\n"); msg_pspew("ExpROMSz=0x%01x\n", (tmp >> 19) & 0x7); /* Enable BAR2 mapping to flash */ - tmp = pci_mmio_readl(mv_bar + PCI_BAR2_CONTROL); + tmp = pci_mmio_readl(bar + PCI_BAR2_CONTROL); msg_pspew("PCI BAR2 (Flash/NVRAM) Control:\n"); msg_pspew("Bar2En=0x%01x\n", (tmp >> 0) & 0x1); msg_pspew("BAR2TransAttr=0x%01x\n", (tmp >> 1) & 0x1f); msg_pspew("BAR2Sz=0x%01x\n", (tmp >> 19) & 0x7); tmp &= 0xffffffc0; tmp |= 0x0000001f; - pci_rmmio_writel(tmp, mv_bar + PCI_BAR2_CONTROL); + pci_rmmio_writel(tmp, bar + PCI_BAR2_CONTROL); /* Enable flash: GPIO Port Control Register 0x104f0 */ - tmp = pci_mmio_readl(mv_bar + GPIO_PORT_CONTROL); + tmp = pci_mmio_readl(bar + GPIO_PORT_CONTROL); msg_pspew("GPIOPortMode=0x%01x\n", (tmp >> 0) & 0x3); if (((tmp >> 0) & 0x3) != 0x2) msg_pinfo("Warning! Either the straps are incorrect or you " @@ -163,7 +178,7 @@ static int satamv_init(void) "values!\n"); tmp &= 0xfffffffc; tmp |= 0x2; - pci_rmmio_writel(tmp, mv_bar + GPIO_PORT_CONTROL); + pci_rmmio_writel(tmp, bar + GPIO_PORT_CONTROL); /* Get I/O BAR location. */ addr = pcidev_readbar(dev, PCI_BASE_ADDRESS_2); @@ -174,13 +189,21 @@ static int satamv_init(void) * FIXME: Check if the I/O BAR is actually reachable. * This is an arch specific check. */ - mv_iobar = addr & 0xffff; - msg_pspew("Activating I/O BAR at 0x%04x\n", mv_iobar); + iobar = addr & 0xffff; + msg_pspew("Activating I/O BAR at 0x%04x\n", iobar); + + struct satamv_data *data = calloc(1, sizeof(*data)); + if (!data) { + msg_perr("Unable to allocate space for PAR master data\n"); + return 1; + } + data->mv_bar = bar; + data->mv_iobar = iobar; /* 512 kByte with two 8-bit latches, and * 4 MByte with additional 3-bit latch. */ max_rom_decode.parallel = 4 * 1024 * 1024; - return register_par_master(&par_master_satamv, BUS_PARALLEL, NULL); + return register_par_master(&par_master_satamv, BUS_PARALLEL, data); } const struct programmer_entry programmer_satamv = { |