diff options
| author | Neil Armstrong <narmstrong@baylibre.com> | 2021-01-27 12:13:35 +0000 |
|---|---|---|
| committer | Anastasia Klimchuk <aklm@chromium.org> | 2023-09-16 08:41:46 +0000 |
| commit | aa468cf0bd49e1da193b47937193b958f646430e (patch) | |
| tree | 276d571960f0ff3ebc2915adfc64ca454a92b897 | |
| parent | 761746754484843c41a2fc1d672e8848cc7afa6a (diff) | |
| download | flashrom-aa468cf0bd49e1da193b47937193b958f646430e.tar.gz flashrom-aa468cf0bd49e1da193b47937193b958f646430e.tar.bz2 flashrom-aa468cf0bd49e1da193b47937193b958f646430e.zip | |
flashchips: add definition of the XT25F02E SPI NOR flash
This adds definition of the XT25F02E 2MBit SPI NOR Flash
from XTX Technology Limited.
Tested (Probe, Erase, Write, Read) with a VL805 USB3.0 bridge.
Datasheet:
https://datasheet.lcsc.com/lcsc/2006091008_XTX-XT25F02EDTIGT_C596313.pdf
Signed-off-by: Neil Armstrong <narmstrong@baylibre.com>
Change-Id: I295633c448c05520e4a6aa09c08bd7c9f2346d54
Signed-off-by: Anastasia Klimchuk <aklm@flashrom.org>
Reviewed-on: https://review.coreboot.org/c/flashrom/+/50263
Reviewed-by: Peter Marheine <pmarheine@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
| -rw-r--r-- | flashchips.c | 35 | ||||
| -rw-r--r-- | include/flashchips.h | 1 |
2 files changed, 36 insertions, 0 deletions
diff --git a/flashchips.c b/flashchips.c index 009624fa0..065ebf298 100644 --- a/flashchips.c +++ b/flashchips.c @@ -21095,6 +21095,41 @@ const struct flashchip flashchips[] = { { .vendor = "XTX Technology Limited", + .name = "XT25F02E", + .bustype = BUS_SPI, + .manufacture_id = XTX_ID, + .model_id = XTX_XT25F02E, + .total_size = 256, + .page_size = 256, + .feature_bits = FEATURE_WRSR_WREN, + .tested = TEST_OK_PREW, + .probe = PROBE_SPI_RDID, + .probe_timing = TIMING_ZERO, + .block_erasers = + { + { + .eraseblocks = { {4 * 1024, 64} }, + .block_erase = SPI_BLOCK_ERASE_20, + }, { + .eraseblocks = { {64 * 1024, 4} }, + .block_erase = SPI_BLOCK_ERASE_D8, + }, { + .eraseblocks = { {256 * 1024, 1} }, + .block_erase = SPI_BLOCK_ERASE_60, + }, { + .eraseblocks = { {256 * 1024, 1} }, + .block_erase = SPI_BLOCK_ERASE_C7, + } + }, + .printlock = SPI_PRETTYPRINT_STATUS_REGISTER_BP1_SRWD, + .unlock = SPI_DISABLE_BLOCKPROTECT_BP1_SRWD, + .write = SPI_CHIP_WRITE256, + .read = SPI_CHIP_READ, + .voltage = {2700, 3600}, + }, + + { + .vendor = "XTX Technology Limited", .name = "XT25F64B", .bustype = BUS_SPI, .manufacture_id = XTX_ID, diff --git a/include/flashchips.h b/include/flashchips.h index 6e191eb1d..8645054dc 100644 --- a/include/flashchips.h +++ b/include/flashchips.h @@ -1045,6 +1045,7 @@ #define WINBOND_W49V002FA 0x32 #define XTX_ID 0x0B /* XTX Technology Limited */ +#define XTX_XT25F02E 0x4012 #define XTX_XT25F64B 0x4017 #define ZETTADEVICE_ID 0xBA /* Zetta Device */ |