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author | Ao Zhong <hacc1225@gmail.com> | 2023-06-14 01:01:50 +0200 |
---|---|---|
committer | Anastasia Klimchuk <aklm@chromium.org> | 2023-07-12 07:42:36 +0000 |
commit | aac723f18418418a804d8e2b93814a0b64d9d544 (patch) | |
tree | 585bd21074cb446ed2e0a8607482580efb204e7a | |
parent | 27a368a23be35b3091c236caa1d0eee9d10b8d10 (diff) | |
download | flashrom-aac723f18418418a804d8e2b93814a0b64d9d544.tar.gz flashrom-aac723f18418418a804d8e2b93814a0b64d9d544.tar.bz2 flashrom-aac723f18418418a804d8e2b93814a0b64d9d544.zip |
flashchips.c: Adding support for ISSI IS25WP020/40/80
This patch added support for IS25WP020, IS25WP040, and IS25WP080
SPI flash chips. The datasheet for these chips can be
found at: https://www.issi.com/WW/pdf/25WP016_080_040_020.pdf
Tested read, write, and erase functions on IS25WP080.
Test log:
Write: https://paste.flashrom.org/view.php?id=3698
Write test 2: https://paste.flashrom.org/view.php?id=3699
Erase: https://paste.flashrom.org/view.php?id=3700
Change-Id: I8a786de5cf9ffefb2d57f89bbab71e289b5c2b28
Signed-off-by: Ao Zhong <hacc1225@gmail.com>
Reviewed-on: https://review.coreboot.org/c/flashrom/+/75830
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Anastasia Klimchuk <aklm@chromium.org>
-rw-r--r-- | flashchips.c | 126 | ||||
-rw-r--r-- | include/flashchips.h | 3 |
2 files changed, 129 insertions, 0 deletions
diff --git a/flashchips.c b/flashchips.c index 9b2a18779..b11c558a0 100644 --- a/flashchips.c +++ b/flashchips.c @@ -7767,6 +7767,48 @@ const struct flashchip flashchips[] = { { .vendor = "ISSI", + .name = "IS25WP020", + .bustype = BUS_SPI, + .manufacture_id = ISSI_ID_SPI, + .model_id = ISSI_IS25WP020, + .total_size = 256, + .page_size = 256, + /* OTP: 1024B total; read 0x48; write 0x42 */ + /* QPI enable 0x35, disable 0xF5 */ + .feature_bits = FEATURE_WRSR_WREN | FEATURE_OTP | FEATURE_QPI, + .tested = TEST_UNTESTED, + .probe = PROBE_SPI_RDID, + .probe_timing = TIMING_ZERO, + .block_erasers = + { + { + .eraseblocks = { {4 * 1024, 64} }, + .block_erase = SPI_BLOCK_ERASE_20, + }, { + .eraseblocks = { {4 * 1024, 64} }, + .block_erase = SPI_BLOCK_ERASE_D7, + }, { + .eraseblocks = { {32 * 1024, 8} }, + .block_erase = SPI_BLOCK_ERASE_52, + }, { + .eraseblocks = { {64 * 1024, 4} }, + .block_erase = SPI_BLOCK_ERASE_D8, + }, { + .eraseblocks = { {256 * 1024, 1} }, + .block_erase = SPI_BLOCK_ERASE_60, + }, { + .eraseblocks = { {256 * 1024, 1} }, + .block_erase = SPI_BLOCK_ERASE_C7, + } + }, + .unlock = SPI_DISABLE_BLOCKPROTECT, + .write = SPI_CHIP_WRITE256, + .read = SPI_CHIP_READ, + .voltage = {1650, 1950}, + }, + + { + .vendor = "ISSI", .name = "IS25WP032", .bustype = BUS_SPI, .manufacture_id = ISSI_ID_SPI, @@ -7809,6 +7851,48 @@ const struct flashchip flashchips[] = { { .vendor = "ISSI", + .name = "IS25WP040", + .bustype = BUS_SPI, + .manufacture_id = ISSI_ID_SPI, + .model_id = ISSI_IS25WP040, + .total_size = 512, + .page_size = 256, + /* OTP: 1024B total; read 0x48; write 0x42 */ + /* QPI enable 0x35, disable 0xF5 */ + .feature_bits = FEATURE_WRSR_WREN | FEATURE_OTP | FEATURE_QPI, + .tested = TEST_UNTESTED, + .probe = PROBE_SPI_RDID, + .probe_timing = TIMING_ZERO, + .block_erasers = + { + { + .eraseblocks = { {4 * 1024, 128} }, + .block_erase = SPI_BLOCK_ERASE_20, + }, { + .eraseblocks = { {4 * 1024, 128} }, + .block_erase = SPI_BLOCK_ERASE_D7, + }, { + .eraseblocks = { {32 * 1024, 16} }, + .block_erase = SPI_BLOCK_ERASE_52, + }, { + .eraseblocks = { {64 * 1024, 8} }, + .block_erase = SPI_BLOCK_ERASE_D8, + }, { + .eraseblocks = { {512 * 1024, 1} }, + .block_erase = SPI_BLOCK_ERASE_60, + }, { + .eraseblocks = { {512 * 1024, 1} }, + .block_erase = SPI_BLOCK_ERASE_C7, + } + }, + .unlock = SPI_DISABLE_BLOCKPROTECT, + .write = SPI_CHIP_WRITE256, + .read = SPI_CHIP_READ, + .voltage = {1650, 1950}, + }, + + { + .vendor = "ISSI", .name = "IS25WP064", .bustype = BUS_SPI, .manufacture_id = ISSI_ID_SPI, @@ -7851,6 +7935,48 @@ const struct flashchip flashchips[] = { { .vendor = "ISSI", + .name = "IS25WP080", + .bustype = BUS_SPI, + .manufacture_id = ISSI_ID_SPI, + .model_id = ISSI_IS25WP080, + .total_size = 1024, + .page_size = 256, + /* OTP: 1024B total; read 0x48; write 0x42 */ + /* QPI enable 0x35, disable 0xF5 */ + .feature_bits = FEATURE_WRSR_WREN | FEATURE_OTP | FEATURE_QPI, + .tested = TEST_OK_PREW, + .probe = PROBE_SPI_RDID, + .probe_timing = TIMING_ZERO, + .block_erasers = + { + { + .eraseblocks = { {4 * 1024, 256} }, + .block_erase = SPI_BLOCK_ERASE_20, + }, { + .eraseblocks = { {4 * 1024, 256} }, + .block_erase = SPI_BLOCK_ERASE_D7, + }, { + .eraseblocks = { {32 * 1024, 32} }, + .block_erase = SPI_BLOCK_ERASE_52, + }, { + .eraseblocks = { {64 * 1024, 16} }, + .block_erase = SPI_BLOCK_ERASE_D8, + }, { + .eraseblocks = { {1024 * 1024, 1} }, + .block_erase = SPI_BLOCK_ERASE_60, + }, { + .eraseblocks = { {1024 * 1024, 1} }, + .block_erase = SPI_BLOCK_ERASE_C7, + } + }, + .unlock = SPI_DISABLE_BLOCKPROTECT, + .write = SPI_CHIP_WRITE256, + .read = SPI_CHIP_READ, + .voltage = {1650, 1950}, + }, + + { + .vendor = "ISSI", .name = "IS25WP128", .bustype = BUS_SPI, .manufacture_id = ISSI_ID_SPI, diff --git a/include/flashchips.h b/include/flashchips.h index 49e54fa00..dd0e83585 100644 --- a/include/flashchips.h +++ b/include/flashchips.h @@ -479,8 +479,11 @@ #define ISSI_IS25LP128 0x6018 #define ISSI_IS25LP256 0x6019 #define ISSI_IS25WP016 0x7015 +#define ISSI_IS25WP020 0x7012 #define ISSI_IS25WP032 0x7016 +#define ISSI_IS25WP040 0x7013 #define ISSI_IS25WP064 0x7017 +#define ISSI_IS25WP080 0x7014 #define ISSI_IS25WP128 0x7018 #define ISSI_IS25WP256 0x7019 #define ISSI_PMC_IS29GL032B 0xF9 |