spi25_statusreg.c: support reading security register

Not to be confused with "secure registers" of OTP.

Security register is a dedicated status register for security-related
bits. You don't write its value directly, issuing special write commands
with no data set separate OTP bits to 1 automatically (WRSCUR, WPSEL
commands). No WREN is necessary, but at least some datasheets indicate
BUSY state after those write commands.

Unlike cases where OTP bit is part of SR and can only be written while
in OTP mode, security register can only be written outside of the mode.

The register is found in at least these chips by Macronix:
 * MX25L6436E
 * MX25L6445E
 * MX25L6465E
 * MX25L6473E

Change-Id: Iae1753ca4cb051127a5bcbeba7f064053adb8dae
Signed-off-by: Sergii Dmytruk <sergii.dmytruk@3mdeb.com>
Reviewed-on: https://review.coreboot.org/c/flashrom/+/59709
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-by: Edward O'Callaghan <quasisec@chromium.org>
Reviewed-by: Nikolai Artemiev <nartemiev@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>

3 files changed, 31 insertions, 0 deletions

diff --git a/include/flash.h b/include/flash.h
index ea8e25b8e..197c11ea1 100644
--- a/include/flash.h
+++ b/include/flash.h
@@ -155,6 +155,12 @@ enum write_granularity {
 #define FEATURE_WRSR_EXT3	((1 << 22) | FEATURE_WRSR_EXT2)
 #define FEATURE_WRSR3		(1 << 23)
 
+/*
+ * Whether chip has security register (RDSCUR/WRSCUR commands).
+ * Not to be confused with "secure registers" of OTP.
+ */
+#define FEATURE_SCUR		(1 << 24)
+
 #define ERASED_VALUE(flash)	(((flash)->chip->feature_bits & FEATURE_ERASED_ZERO) ? 0x00 : 0xff)
 #define UNERASED_VALUE(flash)	(((flash)->chip->feature_bits & FEATURE_ERASED_ZERO) ? 0xff : 0x00)
 
@@ -189,6 +195,7 @@ enum flash_reg {
 	STATUS1,
 	STATUS2,
 	STATUS3,
+	SECURITY,
 	MAX_REGISTERS
 };
 
diff --git a/include/spi.h b/include/spi.h
index 9b38cab64..c77866c41 100644
--- a/include/spi.h
+++ b/include/spi.h
@@ -167,6 +167,16 @@
 #define JEDEC_WRSR3_OUTSIZE	0x02
 #define JEDEC_WRSR3_INSIZE	0x00
 
+/* Read Security Register */
+#define JEDEC_RDSCUR		0x2b
+#define JEDEC_RDSCUR_OUTSIZE	0x01
+#define JEDEC_RDSCUR_INSIZE	0x01
+
+/* Write Security Register */
+#define JEDEC_WRSCUR		0x2f
+#define JEDEC_WRSCUR_OUTSIZE	0x01
+#define JEDEC_WRSCUR_INSIZE	0x00
+
 /* Enter 4-byte Address Mode */
 #define JEDEC_ENTER_4_BYTE_ADDR_MODE	0xB7
 
diff --git a/spi25_statusreg.c b/spi25_statusreg.c
index d0ce8597a..2859b2320 100644
--- a/spi25_statusreg.c
+++ b/spi25_statusreg.c
@@ -100,6 +100,13 @@ int spi_write_register(const struct flashctx *flash, enum flash_reg reg, uint8_t
 		}
 		msg_cerr("Cannot write SR3: unsupported by chip\n");
 		return 1;
+	case SECURITY:
+		/*
+		 * Security register doesn't have a normal write operation. Instead,
+		 * there are separate commands that set individual OTP bits.
+		 */
+		msg_cerr("Cannot write SECURITY: unsupported by design\n");
+		return 1;
 	default:
 		msg_cerr("Cannot write register: unknown register\n");
 		return 1;
@@ -195,6 +202,13 @@ int spi_read_register(const struct flashctx *flash, enum flash_reg reg, uint8_t
 		}
 		msg_cerr("Cannot read SR3: unsupported by chip\n");
 		return 1;
+	case SECURITY:
+		if (feature_bits & FEATURE_SCUR) {
+			read_cmd = JEDEC_RDSCUR;
+			break;
+		}
+		msg_cerr("Cannot read SECURITY: unsupported by chip\n");
+		return 1;
 	default:
 		msg_cerr("Cannot read register: unknown register\n");
 		return 1;