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| author | Edward O'Callaghan <quasisec@google.com> | 2020-12-02 13:17:46 +1100 |
|---|---|---|
| committer | Felix Singer <felixsinger@posteo.net> | 2022-09-29 17:04:06 +0000 |
| commit | fd42af008714bb608b6223dd87d7424897eab020 (patch) | |
| tree | f37943c78f637f01de90e053e453791f220e48f8 | |
| parent | b67c15b90e025ce09cfa922de59a2f9e05bea0f4 (diff) | |
| download | flashrom-fd42af008714bb608b6223dd87d7424897eab020.tar.gz flashrom-fd42af008714bb608b6223dd87d7424897eab020.tar.bz2 flashrom-fd42af008714bb608b6223dd87d7424897eab020.zip | |
chipset_enable.c: Validate physmap() return rcrb value
Validate the physical mapping in enable_flash_silvermont().
Change-Id: Icc5a799a06b3f310d9a191fa5eb99b255b20d79d
Signed-off-by: Edward O'Callaghan <quasisec@google.com>
Reviewed-on: https://review.coreboot.org/c/flashrom/+/48225
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Sam McNally <sammc@google.com>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/c/flashrom/+/67843
Reviewed-by: Felix Singer <felixsinger@posteo.net>
Reviewed-by: Edward O'Callaghan <quasisec@chromium.org>
| -rw-r--r-- | chipset_enable.c | 2 |
1 files changed, 2 insertions, 0 deletions
diff --git a/chipset_enable.c b/chipset_enable.c index 67ce7614a..6220416b4 100644 --- a/chipset_enable.c +++ b/chipset_enable.c @@ -920,6 +920,8 @@ static int enable_flash_silvermont(struct pci_dev *dev, const char *name) /* Handle GCS (in RCRB) */ void *rcrb = physmap("BYT RCRB", rcba, 4); + if (rcrb == ERROR_PTR) + return ERROR_FATAL; enable_flash_ich_report_gcs(dev, ich_generation, rcrb); physunmap(rcrb, 4); |