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author | Shiyu Sun <sshiyu@google.com> | 2020-10-07 00:42:59 +1100 |
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committer | Edward O'Callaghan <quasisec@chromium.org> | 2020-10-14 09:28:27 +0000 |
commit | 8a99a6e210edfb037571bdc5019ca3b224012c03 (patch) | |
tree | f2a42068e1dcff034e2780d1f7e2ffab617a3ce1 /bitbang_spi.c | |
parent | d4d3657b4d64b8fa38eb05ab2a50fdea3e1b45a4 (diff) | |
download | flashrom-8a99a6e210edfb037571bdc5019ca3b224012c03.tar.gz flashrom-8a99a6e210edfb037571bdc5019ca3b224012c03.tar.bz2 flashrom-8a99a6e210edfb037571bdc5019ca3b224012c03.zip |
realtek_mst_i2c_spi.c: Update GPIO pin 88 toggle function
Here we provide a helper function to allow indexing MCU configuration
registers. The 0x9F port allows access to these MCU configuration
registers followed by the high and then low bytes of the register
address we wish to index written into 0xF5 or 0xF4 respectively, a
read or write can then be made via 0xF5.
For the configuration of GPIO pins on the chip, there are two relevant
register address, 0x104F for pin direction (sink input or push-pull
in-out) configuration and 0xFE3F for pin data values (1 to push-pull
and 0 to sink). The reference design uses GPIO 88 to strap the
write protection pin and so we provide a function that allows the call
site to toggle this state and therefore de-assert hardware write
protection of the external spi flash.
BUG=b:152558985,b:148745673
BRANCH=none
TEST=builds && verified the write protection get disabled.
Change-Id: I1aed0086f917e31bebb51857ad5cce138158fe82
Signed-off-by: Shiyu Sun <sshiyu@chromium.org>
Reviewed-on: https://review.coreboot.org/c/flashrom/+/46089
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-by: Edward O'Callaghan <quasisec@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Diffstat (limited to 'bitbang_spi.c')
0 files changed, 0 insertions, 0 deletions