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| author | Angel Pons <th3fanbus@gmail.com> | 2020-07-10 17:04:10 +0200 |
|---|---|---|
| committer | David Hendricks <david.hendricks@gmail.com> | 2021-05-16 23:14:00 +0000 |
| commit | 11a35980defbf800e33e77cc7a82e89c33865b25 (patch) | |
| tree | dd7ec6f9adb196103cf4fc7a5e57647346ed6632 /chipset_enable.c | |
| parent | 90739d147f1d9b90789873fdbe74da6c616cad6b (diff) | |
| download | flashrom-11a35980defbf800e33e77cc7a82e89c33865b25.tar.gz flashrom-11a35980defbf800e33e77cc7a82e89c33865b25.tar.bz2 flashrom-11a35980defbf800e33e77cc7a82e89c33865b25.zip | |
Add Gemini Lake support
The SPI hardware is pretty much unchanged from Apollo Lake. However, the
IFD differs significantly enough to require special handling.
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Change-Id: Ib5dcdf204166f44a8531c19b5f363b851d2ccd77
Reviewed-on: https://review.coreboot.org/c/flashrom/+/54276
Reviewed-by: Edward O'Callaghan <quasisec@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Diffstat (limited to 'chipset_enable.c')
| -rw-r--r-- | chipset_enable.c | 9 |
1 files changed, 9 insertions, 0 deletions
diff --git a/chipset_enable.c b/chipset_enable.c index 259902eaa..025203cb5 100644 --- a/chipset_enable.c +++ b/chipset_enable.c @@ -601,6 +601,7 @@ static enum chipbustype enable_flash_ich_report_gcs( case CHIPSET_300_SERIES_CANNON_POINT: case CHIPSET_400_SERIES_COMET_POINT: case CHIPSET_APOLLO_LAKE: + case CHIPSET_GEMINI_LAKE: reg_name = "BIOS_SPI_BC"; gcs = pci_read_long(dev, 0xdc); bild = (gcs >> 7) & 1; @@ -699,6 +700,7 @@ static enum chipbustype enable_flash_ich_report_gcs( boot_straps = boot_straps_pch8_lp; break; case CHIPSET_APOLLO_LAKE: + case CHIPSET_GEMINI_LAKE: boot_straps = boot_straps_apl; break; case CHIPSET_8_SERIES_WELLSBURG: // FIXME: check datasheet @@ -726,6 +728,7 @@ static enum chipbustype enable_flash_ich_report_gcs( case CHIPSET_300_SERIES_CANNON_POINT: case CHIPSET_400_SERIES_COMET_POINT: case CHIPSET_APOLLO_LAKE: + case CHIPSET_GEMINI_LAKE: bbs = (gcs >> 6) & 0x1; break; default: @@ -976,6 +979,11 @@ static int enable_flash_apl(struct pci_dev *const dev, const char *const name) return enable_flash_pch100_or_c620(dev, name, 0x0d, 2, CHIPSET_APOLLO_LAKE); } +static int enable_flash_glk(struct pci_dev *const dev, const char *const name) +{ + return enable_flash_pch100_or_c620(dev, name, 0x0d, 2, CHIPSET_GEMINI_LAKE); +} + /* Silvermont architecture: Bay Trail(-T/-I), Avoton/Rangeley. * These have a distinctly different behavior compared to other Intel chipsets and hence are handled separately. * @@ -2076,6 +2084,7 @@ const struct penable chipset_enables[] = { {0x8086, 0xa2d2, B_S, NT, "Intel", "X299", enable_flash_pch100}, {0x8086, 0x5ae8, B_S, DEP, "Intel", "Apollo Lake", enable_flash_apl}, {0x8086, 0x5af0, B_S, DEP, "Intel", "Apollo Lake", enable_flash_apl}, + {0x8086, 0x31e8, B_S, DEP, "Intel", "Gemini Lake", enable_flash_glk}, {0x8086, 0xa303, B_S, NT, "Intel", "H310", enable_flash_pch300}, {0x8086, 0xa304, B_S, NT, "Intel", "H370", enable_flash_pch300}, {0x8086, 0xa305, B_S, NT, "Intel", "Z390", enable_flash_pch300}, |