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| author | Sophie van Soest <sophie@entropie.rocks> | 2021-07-04 13:54:26 +0200 |
|---|---|---|
| committer | Angel Pons <th3fanbus@gmail.com> | 2021-09-13 11:07:18 +0000 |
| commit | 1f28ac646fee0a8b75d5b4ec328f048124de3d00 (patch) | |
| tree | 0717cbc29af8c4a8f9af229d85544e9ada9ee61f /chipset_enable.c | |
| parent | 1bc3c5127fc61f3f7d0b9cbed28f0cd458ee1e9b (diff) | |
| download | flashrom-1f28ac646fee0a8b75d5b4ec328f048124de3d00.tar.gz flashrom-1f28ac646fee0a8b75d5b4ec328f048124de3d00.tar.bz2 flashrom-1f28ac646fee0a8b75d5b4ec328f048124de3d00.zip | |
chipset_enable.c: Mark Z97 as DEP
Tested on GIGABYTE GA-Z97-HD3.
Signed-off-by: Sophie van Soest <sophie@entropie.rocks>
Change-Id: I73bdd9afefae8e7c013d400e17a15e56d84322f4
Reviewed-on: https://review.coreboot.org/c/flashrom/+/56060
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-by: Michael Niewöhner <foss@mniewoehner.de>
Diffstat (limited to 'chipset_enable.c')
| -rw-r--r-- | chipset_enable.c | 2 |
1 files changed, 1 insertions, 1 deletions
diff --git a/chipset_enable.c b/chipset_enable.c index 110d7a9e4..cb0fbf115 100644 --- a/chipset_enable.c +++ b/chipset_enable.c @@ -1969,7 +1969,7 @@ const struct penable chipset_enables[] = { {0x8086, 0x8cc1, B_FS, NT, "Intel", "9 Series", enable_flash_pch9}, {0x8086, 0x8cc2, B_FS, NT, "Intel", "9 Series Engineering Sample", enable_flash_pch9}, {0x8086, 0x8cc3, B_FS, NT, "Intel", "9 Series", enable_flash_pch9}, - {0x8086, 0x8cc4, B_FS, NT, "Intel", "Z97", enable_flash_pch9}, + {0x8086, 0x8cc4, B_FS, DEP, "Intel", "Z97", enable_flash_pch9}, {0x8086, 0x8cc6, B_FS, NT, "Intel", "H97", enable_flash_pch9}, {0x8086, 0x8d40, B_FS, NT, "Intel", "C610/X99 (Wellsburg)", enable_flash_pch8_wb}, {0x8086, 0x8d41, B_FS, NT, "Intel", "C610/X99 (Wellsburg)", enable_flash_pch8_wb}, |