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authorGaggery Tsai <gaggery.tsai@intel.com>2019-12-12 11:52:03 -0800
committerNico Huber <nico.h@gmx.de>2021-04-26 16:08:56 +0000
commit4fc21c06098c43fe593f4f6a66910a012a136fd6 (patch)
tree1a51a67350aca15676eae5ba81de5c207d2d3229 /chipset_enable.c
parentd6c7f21a383f695882b2de20cf7e71e73ad52aec (diff)
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chipset_enable.c: Add CMP-H IDs
This patch adds CMP-H support. They are HM470, WM490, QM480, W480, H470, Z490 and Q470. TEST=build flashrom and run on CML-S with CMP-H flashrom -p internal -w ./coreboot.rom reboot and check the code is flashed correctly Signed-off-by: Gaggery Tsai <gaggery.tsai@intel.com> Change-Id: Ic7f04fc5cbe3422cbd219c46586c32fc847c921f Reviewed-on: https://review.coreboot.org/c/flashrom/+/37677 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Angel Pons <th3fanbus@gmail.com> Reviewed-by: Tim Crawford <tcrawford@system76.com> Reviewed-by: Nico Huber <nico.h@gmx.de>
Diffstat (limited to 'chipset_enable.c')
-rw-r--r--chipset_enable.c7
1 files changed, 7 insertions, 0 deletions
diff --git a/chipset_enable.c b/chipset_enable.c
index 4e52092dd..5a1129d4b 100644
--- a/chipset_enable.c
+++ b/chipset_enable.c
@@ -2085,6 +2085,13 @@ const struct penable chipset_enables[] = {
{0x8086, 0xa30d, B_S, NT, "Intel", "HM370", enable_flash_pch300},
{0x8086, 0xa30e, B_S, DEP, "Intel", "CM246", enable_flash_pch300},
{0x8086, 0x3482, B_S, DEP, "Intel", "Ice Lake U Premium", enable_flash_pch300},
+ {0x8086, 0x0684, B_S, NT, "Intel", "H470", enable_flash_pch400},
+ {0x8086, 0x0685, B_S, NT, "Intel", "Z490", enable_flash_pch400},
+ {0x8086, 0x0687, B_S, NT, "Intel", "Q470", enable_flash_pch400},
+ {0x8086, 0x068c, B_S, NT, "Intel", "QM480", enable_flash_pch400},
+ {0x8086, 0x068d, B_S, NT, "Intel", "HM470", enable_flash_pch400},
+ {0x8086, 0x068e, B_S, NT, "Intel", "WM490", enable_flash_pch400},
+ {0x8086, 0x0697, B_S, NT, "Intel", "W480", enable_flash_pch400},
#endif
{0},
};