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| author | Jan Samek <jan.samek@siemens.com> | 2022-12-06 16:42:56 +0100 |
|---|---|---|
| committer | Anastasia Klimchuk <aklm@chromium.org> | 2023-01-18 21:13:56 +0000 |
| commit | 7cab790a46f8459789e258a106e743275e306a2d (patch) | |
| tree | c5f22de878c478fb8bddbf836a37733ae0b277a6 /chipset_enable.c | |
| parent | 58888f78f3690e6701a717cdc65562fdf9038e1e (diff) | |
| download | flashrom-7cab790a46f8459789e258a106e743275e306a2d.tar.gz flashrom-7cab790a46f8459789e258a106e743275e306a2d.tar.bz2 flashrom-7cab790a46f8459789e258a106e743275e306a2d.zip | |
chipset_enable.c: add PCI ID for TGL-UP3
Add PCI ID for the Tiger Lake UP3 (Industrial SKU) SoC.
Change-Id: Ie93af14eb5857bfe51964f6565e475b6249dd407
Signed-off-by: Jan Samek <jan.samek@siemens.com>
Reviewed-on: https://review.coreboot.org/c/flashrom/+/70388
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-by: Anastasia Klimchuk <aklm@chromium.org>
Diffstat (limited to 'chipset_enable.c')
| -rw-r--r-- | chipset_enable.c | 1 |
1 files changed, 1 insertions, 0 deletions
diff --git a/chipset_enable.c b/chipset_enable.c index b9144d195..480113a69 100644 --- a/chipset_enable.c +++ b/chipset_enable.c @@ -2080,6 +2080,7 @@ const struct penable chipset_enables[] = { {0x8086, 0x0284, B_S, DEP, "Intel", "Comet Lake U Premium", enable_flash_pch400}, {0x8086, 0x0285, B_S, DEP, "Intel", "Comet Lake U Base", enable_flash_pch400}, {0x8086, 0xa082, B_S, DEP, "Intel", "Tiger Lake U Premium", enable_flash_pch500}, + {0x8086, 0xa088, B_S, DEP, "Intel", "Tiger Lake UP3", enable_flash_pch500}, {0x8086, 0xa141, B_S, NT, "Intel", "Sunrise Point Desktop Sample", enable_flash_pch100}, {0x8086, 0xa142, B_S, NT, "Intel", "Sunrise Point Unknown Sample", enable_flash_pch100}, {0x8086, 0xa143, B_S, DEP, "Intel", "H110", enable_flash_pch100}, |