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| author | Subrata Banik <subratabanik@google.com> | 2022-03-14 14:17:32 +0530 |
|---|---|---|
| committer | Edward O'Callaghan <quasisec@chromium.org> | 2022-03-30 21:18:11 +0000 |
| commit | 7dcd0deafe667fdbec529285077149e0832acd69 (patch) | |
| tree | 3a3258e8d6940b21f48e2996e073404643e84367 /chipset_enable.c | |
| parent | 1b66464269ed829ba08b2736500712e50753cfab (diff) | |
| download | flashrom-7dcd0deafe667fdbec529285077149e0832acd69.tar.gz flashrom-7dcd0deafe667fdbec529285077149e0832acd69.tar.bz2 flashrom-7dcd0deafe667fdbec529285077149e0832acd69.zip | |
ichspi: Add support for Meteor Lake
This patch adds Meteor Lake support into flashrom.
Additionally, utilize CSSO (CPU Soft Strap Offset) to uniquely detect
the chipset when the CSSL (CPU Soft Strap Length) field default value
(0x03) on Meteor Lake is the same as Elkhart Lake.
BUG=b:224325352
TEST=Flashrom is able to detect MTL SPI DID and show chipset name as below:
> flashrom --flash-name
....
Found chipset "Intel Meteor Lake-P/M".
....
> flashrom - internal --ifd -i fd -i bios -r /tmp/bios.rom
....
Reading ich_descriptor... done.
Assuming chipset 'Meteor Lake'.
Using regions: "bios", "fd".
Reading flash... done.
SUCCESS
Signed-off-by: Subrata Banik <subratabanik@google.com>
Change-Id: I0a2ffe2ba8d96c90d89b77e0d8583d179ff02a75
Reviewed-on: https://review.coreboot.org/c/flashrom/+/62783
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Edward O'Callaghan <quasisec@chromium.org>
Reviewed-by: Wonkyu Kim <wonkyu.kim@intel.com>
Reviewed-by: Sam McNally <sammc@google.com>
Diffstat (limited to 'chipset_enable.c')
| -rw-r--r-- | chipset_enable.c | 9 |
1 files changed, 9 insertions, 0 deletions
diff --git a/chipset_enable.c b/chipset_enable.c index 1cb170088..b050f642d 100644 --- a/chipset_enable.c +++ b/chipset_enable.c @@ -606,6 +606,7 @@ static enum chipbustype enable_flash_ich_report_gcs( case CHIPSET_400_SERIES_COMET_POINT: case CHIPSET_500_SERIES_TIGER_POINT: case CHIPSET_600_SERIES_ALDER_POINT: + case CHIPSET_METEOR_LAKE: case CHIPSET_ELKHART_LAKE: case CHIPSET_APOLLO_LAKE: case CHIPSET_GEMINI_LAKE: @@ -711,6 +712,7 @@ static enum chipbustype enable_flash_ich_report_gcs( break; case CHIPSET_500_SERIES_TIGER_POINT: case CHIPSET_600_SERIES_ALDER_POINT: + case CHIPSET_METEOR_LAKE: boot_straps = boot_straps_pch500; break; case CHIPSET_APOLLO_LAKE: @@ -744,6 +746,7 @@ static enum chipbustype enable_flash_ich_report_gcs( case CHIPSET_400_SERIES_COMET_POINT: case CHIPSET_500_SERIES_TIGER_POINT: case CHIPSET_600_SERIES_ALDER_POINT: + case CHIPSET_METEOR_LAKE: case CHIPSET_APOLLO_LAKE: case CHIPSET_GEMINI_LAKE: case CHIPSET_ELKHART_LAKE: @@ -1002,6 +1005,11 @@ static int enable_flash_pch600(struct pci_dev *const dev, const char *const name return enable_flash_pch100_or_c620(dev, name, 0x1f, 5, CHIPSET_600_SERIES_ALDER_POINT); } +static int enable_flash_mtl(struct pci_dev *const dev, const char *const name) +{ + return enable_flash_pch100_or_c620(dev, name, 0x1f, 5, CHIPSET_METEOR_LAKE); +} + static int enable_flash_mcc(struct pci_dev *const dev, const char *const name) { return enable_flash_pch100_or_c620(dev, name, 0x1f, 5, CHIPSET_ELKHART_LAKE); @@ -2151,6 +2159,7 @@ const struct penable chipset_enables[] = { {0x8086, 0x438b, B_S, DEP, "Intel", "HM570", enable_flash_pch500}, {0x8086, 0x54a4, B_S, DEP, "Intel", "Alder Lake-N", enable_flash_pch600}, {0x8086, 0x51a4, B_S, DEP, "Intel", "Alder Lake-P", enable_flash_pch600}, + {0x8086, 0x7e23, B_S, DEP, "Intel", "Meteor Lake-P/M", enable_flash_mtl}, #endif {0}, }; |