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| author | Michał Żygowski <michal.zygowski@3mdeb.com> | 2021-06-16 15:13:54 +0200 |
|---|---|---|
| committer | Nico Huber <nico.h@gmx.de> | 2021-11-17 12:11:17 +0000 |
| commit | 93b01904db607ef8169047e68e376dcda1bd7fbe (patch) | |
| tree | e57bbe3307e6901bb0d084158877b4188be96fbe /chipset_enable.c | |
| parent | 5020cf3a6216879a1c07141bd15bc19044158767 (diff) | |
| download | flashrom-93b01904db607ef8169047e68e376dcda1bd7fbe.tar.gz flashrom-93b01904db607ef8169047e68e376dcda1bd7fbe.tar.bz2 flashrom-93b01904db607ef8169047e68e376dcda1bd7fbe.zip | |
Add Tiger Lake U Premium support
Tiger Lake has very low ICCRIBA (TGL=0x11, CNL=0x34 and CML=0x34) and
detects as unknown chipset compatible with 300 series chipset. Add a
new enum CHIPSET_500_SERIES_TIGER_POINT and treat it identically to
CHIPSET_400_SERIES_COMET_POINT. There are some exceptions though,
ICCRIBA is no longer present n descriptor content so a new union has
been defined for new fields and used in descriptor guessing.
freq_read field is not present on Tiger Lake, moreover in CannonPoint
and Comet Point this field is used as eSPI/EC frequency, so a new
function to print read frequency has ben added. Finally Tiger lake
boot straps include eSPI, so a new bus has been added for the new
straps.
TEST=Flash BIOS region on Intel i5-1135G7
Signed-off-by: Michał Żygowski <michal.zygowski@3mdeb.com>
Change-Id: I28f3b6fe9f8ce9e976a6808683f46b6f4ec72bdd
Reviewed-on: https://review.coreboot.org/c/flashrom/+/55578
Reviewed-by: Nico Huber <nico.h@gmx.de>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Diffstat (limited to 'chipset_enable.c')
| -rw-r--r-- | chipset_enable.c | 14 |
1 files changed, 14 insertions, 0 deletions
diff --git a/chipset_enable.c b/chipset_enable.c index cb0fbf115..26db472ad 100644 --- a/chipset_enable.c +++ b/chipset_enable.c @@ -600,6 +600,7 @@ static enum chipbustype enable_flash_ich_report_gcs( case CHIPSET_C620_SERIES_LEWISBURG: case CHIPSET_300_SERIES_CANNON_POINT: case CHIPSET_400_SERIES_COMET_POINT: + case CHIPSET_500_SERIES_TIGER_POINT: case CHIPSET_APOLLO_LAKE: case CHIPSET_GEMINI_LAKE: reg_name = "BIOS_SPI_BC"; @@ -653,6 +654,9 @@ static enum chipbustype enable_flash_ich_report_gcs( static const struct boot_straps boot_straps_pch8_lp[] = { { "SPI", BUS_SPI }, { "LPC", BUS_LPC | BUS_FWH } }; + static const struct boot_straps boot_straps_pch500[] = + { { "SPI", BUS_SPI }, + { "eSPI", BUS_NONE } }; static const struct boot_straps boot_straps_apl[] = { { "SPI", BUS_SPI }, { "reserved", BUS_NONE } }; @@ -699,6 +703,9 @@ static enum chipbustype enable_flash_ich_report_gcs( case CHIPSET_400_SERIES_COMET_POINT: boot_straps = boot_straps_pch8_lp; break; + case CHIPSET_500_SERIES_TIGER_POINT: + boot_straps = boot_straps_pch500; + break; case CHIPSET_APOLLO_LAKE: case CHIPSET_GEMINI_LAKE: boot_straps = boot_straps_apl; @@ -727,6 +734,7 @@ static enum chipbustype enable_flash_ich_report_gcs( case CHIPSET_C620_SERIES_LEWISBURG: case CHIPSET_300_SERIES_CANNON_POINT: case CHIPSET_400_SERIES_COMET_POINT: + case CHIPSET_500_SERIES_TIGER_POINT: case CHIPSET_APOLLO_LAKE: case CHIPSET_GEMINI_LAKE: bbs = (gcs >> 6) & 0x1; @@ -974,6 +982,11 @@ static int enable_flash_pch400(struct pci_dev *const dev, const char *const name return enable_flash_pch100_or_c620(dev, name, 0x1f, 5, CHIPSET_400_SERIES_COMET_POINT); } +static int enable_flash_pch500(struct pci_dev *const dev, const char *const name) +{ + return enable_flash_pch100_or_c620(dev, name, 0x1f, 5, CHIPSET_500_SERIES_TIGER_POINT); +} + static int enable_flash_apl(struct pci_dev *const dev, const char *const name) { return enable_flash_pch100_or_c620(dev, name, 0x0d, 2, CHIPSET_APOLLO_LAKE); @@ -2029,6 +2042,7 @@ const struct penable chipset_enables[] = { {0x8086, 0x9d84, B_S, DEP, "Intel", "Cannon Lake U Premium", enable_flash_pch300}, {0x8086, 0x0284, B_S, DEP, "Intel", "Comet Lake U Premium", enable_flash_pch400}, {0x8086, 0x0285, B_S, DEP, "Intel", "Comet Lake U Base", enable_flash_pch400}, + {0x8086, 0xa082, B_S, DEP, "Intel", "Tiger Lake U Premium", enable_flash_pch500}, {0x8086, 0xa141, B_S, NT, "Intel", "Sunrise Point Desktop Sample", enable_flash_pch100}, {0x8086, 0xa142, B_S, NT, "Intel", "Sunrise Point Unknown Sample", enable_flash_pch100}, {0x8086, 0xa143, B_S, DEP, "Intel", "H110", enable_flash_pch100}, |