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| author | David Hendricks <dhendricks@fb.com> | 2017-08-08 20:02:22 -0700 |
|---|---|---|
| committer | David Hendricks <david.hendricks@gmail.com> | 2017-09-01 20:34:44 +0000 |
| commit | a5216367d5640f07d58a6549fa6df86d91daff1a (patch) | |
| tree | 72cb2a7ba167ed6d6e0509ad8292ea7283932e7a /chipset_enable.c | |
| parent | aa91d5c16858cb400cc61e8a759838f645e3f314 (diff) | |
| download | flashrom-a5216367d5640f07d58a6549fa6df86d91daff1a.tar.gz flashrom-a5216367d5640f07d58a6549fa6df86d91daff1a.tar.bz2 flashrom-a5216367d5640f07d58a6549fa6df86d91daff1a.zip | |
chipset_enable: Add support for C620-series Lewisburg PCH
This adds PCI IDs for C620-series PCHs and adds
CHIPSET_C620_SERIES_LEWISBURG as a new entry in the ich_chipset enum.
Lewisburg is very similar to Sunrise Point for Flashrom's purposes,
however one important difference is the way the "number of masters" is
interpreted from the flash descriptor (0-based vs. 1-based). There are
also new flash regions defined.
Change-Id: I96c89bc28bdfcd953229c17679f2c28f8b874d0b
Signed-off-by: David Hendricks <dhendricks@fb.com>
Reviewed-on: https://review.coreboot.org/20922
Reviewed-by: Nico Huber <nico.h@gmx.de>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Diffstat (limited to 'chipset_enable.c')
| -rw-r--r-- | chipset_enable.c | 29 |
1 files changed, 27 insertions, 2 deletions
diff --git a/chipset_enable.c b/chipset_enable.c index 36e2838f4..a3b7f8dd6 100644 --- a/chipset_enable.c +++ b/chipset_enable.c @@ -601,6 +601,7 @@ static void enable_flash_ich_report_gcs(struct pci_dev *const dev, const enum ic top_swap = (gcs & 2) >> 1; break; case CHIPSET_100_SERIES_SUNRISE_POINT: + case CHIPSET_C620_SERIES_LEWISBURG: reg_name = "BIOS_SPI_BC"; gcs = pci_read_long(dev, 0xdc); bild = (gcs >> 7) & 1; @@ -658,6 +659,7 @@ static void enable_flash_ich_report_gcs(struct pci_dev *const dev, const enum ic case CHIPSET_8_SERIES_LYNX_POINT_LP: case CHIPSET_9_SERIES_WILDCAT_POINT_LP: case CHIPSET_100_SERIES_SUNRISE_POINT: + case CHIPSET_C620_SERIES_LEWISBURG: straps_names = straps_names_pch8_lp; break; case CHIPSET_8_SERIES_WELLSBURG: // FIXME: check datasheet @@ -681,6 +683,7 @@ static void enable_flash_ich_report_gcs(struct pci_dev *const dev, const enum ic bbs = (gcs >> 10) & 0x1; break; case CHIPSET_100_SERIES_SUNRISE_POINT: + case CHIPSET_C620_SERIES_LEWISBURG: bbs = (gcs >> 6) & 0x1; break; default: @@ -830,9 +833,8 @@ static int enable_flash_pch100_shutdown(void *const pci_acc) return 0; } -static int enable_flash_pch100(struct pci_dev *const dev, const char *const name) +static int enable_flash_pch100_or_c620(struct pci_dev *const dev, const char *const name, const enum ich_chipset pch_generation) { - const enum ich_chipset pch_generation = CHIPSET_100_SERIES_SUNRISE_POINT; int ret = ERROR_FATAL; /* @@ -888,6 +890,16 @@ _freepci_ret: return ret; } +static int enable_flash_pch100(struct pci_dev *const dev, const char *const name) +{ + return enable_flash_pch100_or_c620(dev, name, CHIPSET_100_SERIES_SUNRISE_POINT); +} + +static int enable_flash_c620(struct pci_dev *const dev, const char *const name) +{ + return enable_flash_pch100_or_c620(dev, name, CHIPSET_C620_SERIES_LEWISBURG); +} + /* Silvermont architecture: Bay Trail(-T/-I), Avoton/Rangeley. * These have a distinctly different behavior compared to other Intel chipsets and hence are handled separately. * @@ -1915,6 +1927,19 @@ const struct penable chipset_enables[] = { {0x8086, 0xa153, NT, "Intel", "QM175", enable_flash_pch100}, {0x8086, 0xa154, NT, "Intel", "CM238", enable_flash_pch100}, {0x8086, 0xa155, NT, "Intel", "QMU185", enable_flash_pch100}, + {0x8086, 0xa1c1, NT, "Intel", "C621 Series Chipset (QS/PRQ)", enable_flash_c620}, + {0x8086, 0xa1c2, NT, "Intel", "C622 Series Chipset (QS/PRQ)", enable_flash_c620}, + {0x8086, 0xa1c3, NT, "Intel", "C624 Series Chipset (QS/PRQ)", enable_flash_c620}, + {0x8086, 0xa1c4, NT, "Intel", "C625 Series Chipset (QS/PRQ)", enable_flash_c620}, + {0x8086, 0xa1c5, NT, "Intel", "C626 Series Chipset (QS/PRQ)", enable_flash_c620}, + {0x8086, 0xa1c6, NT, "Intel", "C627 Series Chipset (QS/PRQ)", enable_flash_c620}, + {0x8086, 0xa1c7, NT, "Intel", "C628 Series Chipset (QS/PRQ)", enable_flash_c620}, + {0x8086, 0xa242, NT, "Intel", "C624 Series Chipset Supersku", enable_flash_c620}, + {0x8086, 0xa243, NT, "Intel", "C627 Series Chipset Supersku", enable_flash_c620}, + {0x8086, 0xa244, NT, "Intel", "C621 Series Chipset Supersku", enable_flash_c620}, + {0x8086, 0xa245, NT, "Intel", "C627 Series Chipset Supersku", enable_flash_c620}, + {0x8086, 0xa246, NT, "Intel", "C628 Series Chipset Supersku", enable_flash_c620}, + {0x8086, 0xa247, NT, "Intel", "C620 Series Chipset Supersku", enable_flash_c620}, #endif {0}, }; |