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| author | Werner Zeh <werner.zeh@siemens.com> | 2022-01-03 09:44:29 +0100 |
|---|---|---|
| committer | Nico Huber <nico.h@gmx.de> | 2022-02-04 12:08:51 +0000 |
| commit | a8be6dace8ace92210c6423ca26c545c8b9e991f (patch) | |
| tree | 93ac84426181ca6c7794b3ad07aadaa79c05b052 /chipset_enable.c | |
| parent | c26f27bef8cde6249dab86f4d46943260734793e (diff) | |
| download | flashrom-a8be6dace8ace92210c6423ca26c545c8b9e991f.tar.gz flashrom-a8be6dace8ace92210c6423ca26c545c8b9e991f.tar.bz2 flashrom-a8be6dace8ace92210c6423ca26c545c8b9e991f.zip | |
Add Elkhart Lake support
Elkhart Lake has a chipset called Mule Creek Canyon which is quite
compatible with 300 series chipsets. There are a few differences though,
e.g. different encoding for the SPI clock values for read and write in
the FLCOMP register. In addition Elkhart Lake has a new PCI device ID
for the SPI controller which is added, too.
TEST=Read and flash complete flash on Siemens MC EHL1
Change-Id: I711e39a3ec9cd7098389231eaa1cb864d615a475
Signed-off-by: Werner Zeh <werner.zeh@siemens.com>
Reviewed-on: https://review.coreboot.org/c/flashrom/+/60711
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Nico Huber <nico.h@gmx.de>
Diffstat (limited to 'chipset_enable.c')
| -rw-r--r-- | chipset_enable.c | 9 |
1 files changed, 9 insertions, 0 deletions
diff --git a/chipset_enable.c b/chipset_enable.c index fe7ec1530..d9a1d3a79 100644 --- a/chipset_enable.c +++ b/chipset_enable.c @@ -605,6 +605,7 @@ static enum chipbustype enable_flash_ich_report_gcs( case CHIPSET_300_SERIES_CANNON_POINT: case CHIPSET_400_SERIES_COMET_POINT: case CHIPSET_500_SERIES_TIGER_POINT: + case CHIPSET_ELKHART_LAKE: case CHIPSET_APOLLO_LAKE: case CHIPSET_GEMINI_LAKE: reg_name = "BIOS_SPI_BC"; @@ -712,6 +713,7 @@ static enum chipbustype enable_flash_ich_report_gcs( break; case CHIPSET_APOLLO_LAKE: case CHIPSET_GEMINI_LAKE: + case CHIPSET_ELKHART_LAKE: boot_straps = boot_straps_apl; break; case CHIPSET_8_SERIES_WELLSBURG: // FIXME: check datasheet @@ -741,6 +743,7 @@ static enum chipbustype enable_flash_ich_report_gcs( case CHIPSET_500_SERIES_TIGER_POINT: case CHIPSET_APOLLO_LAKE: case CHIPSET_GEMINI_LAKE: + case CHIPSET_ELKHART_LAKE: bbs = (gcs >> 6) & 0x1; break; default: @@ -991,6 +994,11 @@ static int enable_flash_pch500(struct pci_dev *const dev, const char *const name return enable_flash_pch100_or_c620(dev, name, 0x1f, 5, CHIPSET_500_SERIES_TIGER_POINT); } +static int enable_flash_mcc(struct pci_dev *const dev, const char *const name) +{ + return enable_flash_pch100_or_c620(dev, name, 0x1f, 5, CHIPSET_ELKHART_LAKE); +} + static int enable_flash_apl(struct pci_dev *const dev, const char *const name) { return enable_flash_pch100_or_c620(dev, name, 0x0d, 2, CHIPSET_APOLLO_LAKE); @@ -2105,6 +2113,7 @@ const struct penable chipset_enables[] = { {0x8086, 0x5af0, B_S, DEP, "Intel", "Apollo Lake", enable_flash_apl}, {0x8086, 0x3197, B_S, NT, "Intel", "Gemini Lake", enable_flash_glk}, {0x8086, 0x31e8, B_S, DEP, "Intel", "Gemini Lake", enable_flash_glk}, + {0x8086, 0x4b24, B_S, DEP, "Intel", "Elkhart Lake", enable_flash_mcc}, {0x8086, 0xa303, B_S, NT, "Intel", "H310", enable_flash_pch300}, {0x8086, 0xa304, B_S, NT, "Intel", "H370", enable_flash_pch300}, {0x8086, 0xa305, B_S, DEP, "Intel", "Z390", enable_flash_pch300}, |