ichspi: Add Jasper Lake support

Additionally, utilize CSSO (CPU Soft Strap Offset) to uniquely detect
the chipset when the CSSL (CPU Soft Strap Length) field default value
(0x03) on Jasper Lake is the same as Elkhart Lake.

BUG=b:221175960
TEST=dedede with `flashrom -p internal --flash-size`.
```
 $ flashrom -VVV -p internal --ifd -i fd -i bios -r /tmp/filename.rom
<snip>
Enabling hardware sequencing by default for 100+ series PCH.
OK.
No board enable found matching coreboot IDs vendor="Google", model="Magolor".
The following protocols are supported: Programmer-specific.
Probing for Programmer Opaque flash chip, 0 kB: Chip identified: GD25Q127C/GD25Q128C
Hardware sequencing reports 1 attached SPI flash chip with a density of 16384 kB.
There is only one partition containing the whole address space (0x000000 - 0xffffff).
There are 4096 erase blocks with 4096 B each.
Added layout entry 00000000 - 00ffffff named complete flash
Found GigaDevice flash chip "GD25Q127C/GD25Q128C" (16384 kB, Programmer-specific) mapped at physical address 0x0000000000000000.
Found GigaDevice flash chip "GD25Q127C/GD25Q128C" (16384 kB, Programmer-specific).
This chip may contain one-time programmable memory. flashrom cannot read
and may never be able to write it, hence it may not be able to completely
clone the contents of this chip (see man page for details).
Reading Status register
Block protection is disabled.
Reading ich descriptor... Reading 4096 bytes starting at 0x000000.
done.
Assuming chipset 'Jasper Lake'.
Added layout entry 00000000 - 00000fff named fd
Added layout entry 00381000 - 00ffffff named bios
Added layout entry 00001000 - 00380fff named me
restore_power_management: Re-enabling power management.
Using regions: "bios", "fd".
Reading Status register
Block protection is disabled.
Reading flash... 0x381000-0xffffff:R Reading 13103104 bytes starting at 0x381000.
000000-0x0fff:R Reading 4096 bytes starting at 0x000000.
done.
restore_power_management: Re-enabling power management.
SUCCESS
Restoring PCI config space for 00:1f:5 reg 0xdc
restore_power_management: Re-enabling power management.
```

Change-Id: Ib942d0b8942fe0a991b2af0b187414818485153d
Signed-off-by: Edward O'Callaghan <quasisec@google.com>
Reviewed-on: https://review.coreboot.org/c/flashrom/+/62282
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Subrata Banik <subratabanik@google.com>
Reviewed-by: Sam McNally <sammc@google.com>

1 files changed, 9 insertions, 0 deletions

diff --git a/chipset_enable.c b/chipset_enable.c
index 27ab12674..a0bffa026 100644
--- a/chipset_enable.c
+++ b/chipset_enable.c
@@ -610,6 +610,7 @@ static enum chipbustype enable_flash_ich_report_gcs(
 	case CHIPSET_ELKHART_LAKE:
 	case CHIPSET_APOLLO_LAKE:
 	case CHIPSET_GEMINI_LAKE:
+	case CHIPSET_JASPER_LAKE:
 		reg_name = "BIOS_SPI_BC";
 		gcs = pci_read_long(dev, 0xdc);
 		bild = (gcs >> 7) & 1;
@@ -717,6 +718,7 @@ static enum chipbustype enable_flash_ich_report_gcs(
 		break;
 	case CHIPSET_APOLLO_LAKE:
 	case CHIPSET_GEMINI_LAKE:
+	case CHIPSET_JASPER_LAKE:
 	case CHIPSET_ELKHART_LAKE:
 		boot_straps = boot_straps_apl;
 		break;
@@ -749,6 +751,7 @@ static enum chipbustype enable_flash_ich_report_gcs(
 	case CHIPSET_METEOR_LAKE:
 	case CHIPSET_APOLLO_LAKE:
 	case CHIPSET_GEMINI_LAKE:
+	case CHIPSET_JASPER_LAKE:
 	case CHIPSET_ELKHART_LAKE:
 		bbs = (gcs >> 6) & 0x1;
 		break;
@@ -1015,6 +1018,11 @@ static int enable_flash_mcc(struct pci_dev *const dev, const char *const name)
 	return enable_flash_pch100_or_c620(dev, name, 0x1f, 5, CHIPSET_ELKHART_LAKE);
 }
 
+static int enable_flash_jsl(struct pci_dev *const dev, const char *const name)
+{
+	return enable_flash_pch100_or_c620(dev, name, 0x1f, 5, CHIPSET_JASPER_LAKE);
+}
+
 static int enable_flash_apl(struct pci_dev *const dev, const char *const name)
 {
 	return enable_flash_pch100_or_c620(dev, name, 0x0d, 2, CHIPSET_APOLLO_LAKE);
@@ -2129,6 +2137,7 @@ const struct penable chipset_enables[] = {
 	{0x8086, 0x5af0, B_S,    DEP, "Intel", "Apollo Lake",			enable_flash_apl},
 	{0x8086, 0x3197, B_S,    NT,  "Intel", "Gemini Lake",			enable_flash_glk},
 	{0x8086, 0x31e8, B_S,    DEP, "Intel", "Gemini Lake",			enable_flash_glk},
+	{0x8086, 0x4da4, B_S,    DEP, "Intel", "Jasper Lake",			enable_flash_jsl},
 	{0x8086, 0x4b24, B_S,    DEP, "Intel", "Elkhart Lake",			enable_flash_mcc},
 	{0x8086, 0xa303, B_S,    NT,  "Intel", "H310",				enable_flash_pch300},
 	{0x8086, 0xa304, B_S,    NT,  "Intel", "H370",				enable_flash_pch300},