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| author | Edward O'Callaghan <quasisec@google.com> | 2020-11-02 14:43:10 +1100 |
|---|---|---|
| committer | Edward O'Callaghan <quasisec@chromium.org> | 2020-11-14 03:27:15 +0000 |
| commit | eeef125b39cc7e19d987b5b40e92b7865dddd19a (patch) | |
| tree | 581f8b8672bf20a3bcd925141b4e050948c5546d /chipset_enable.c | |
| parent | 1b4de5c600f333ef32706db8d2883642b078f8bd (diff) | |
| download | flashrom-eeef125b39cc7e19d987b5b40e92b7865dddd19a.tar.gz flashrom-eeef125b39cc7e19d987b5b40e92b7865dddd19a.tar.bz2 flashrom-eeef125b39cc7e19d987b5b40e92b7865dddd19a.zip | |
chipset_enable.c: Add Intel pch7 did=0x1e4{1,2,3} support
Modified to be pch7 over pch6 as per-coreboot and review
comments.
BUG=none
BRANCH=none
TEST=none
Change-Id: Ic69dc024e9af0c43d6b3a8213a5dc5d2f898c447
Signed-off-by: Edward O'Callaghan <quasisec@google.com>
Reviewed-on: https://review.coreboot.org/c/flashrom/+/47090
Reviewed-by: Sam McNally <sammc@google.com>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Diffstat (limited to 'chipset_enable.c')
| -rw-r--r-- | chipset_enable.c | 3 |
1 files changed, 3 insertions, 0 deletions
diff --git a/chipset_enable.c b/chipset_enable.c index 427347868..04ff9d81e 100644 --- a/chipset_enable.c +++ b/chipset_enable.c @@ -1838,6 +1838,9 @@ const struct penable chipset_enables[] = { {0x8086, 0x1c5c, B_FS, DEP, "Intel", "H61", enable_flash_pch6}, {0x8086, 0x1d40, B_FS, DEP, "Intel", "C60x/X79", enable_flash_pch6}, {0x8086, 0x1d41, B_FS, DEP, "Intel", "C60x/X79", enable_flash_pch6}, + {0x8086, 0x1e41, B_FS, DEP, "Intel", "Desktop Sample", enable_flash_pch7}, + {0x8086, 0x1e42, B_FS, DEP, "Intel", "Mobile Sample", enable_flash_pch7}, + {0x8086, 0x1e43, B_FS, DEP, "Intel", "SFF Sample", enable_flash_pch7}, {0x8086, 0x1e44, B_FS, DEP, "Intel", "Z77", enable_flash_pch7}, {0x8086, 0x1e46, B_FS, NT, "Intel", "Z75", enable_flash_pch7}, {0x8086, 0x1e47, B_FS, DEP, "Intel", "Q77", enable_flash_pch7}, |