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| author | Edward O'Callaghan <quasisec@google.com> | 2020-09-21 17:10:21 +1000 |
|---|---|---|
| committer | Edward O'Callaghan <quasisec@chromium.org> | 2020-09-28 06:32:22 +0000 |
| commit | d3b6acffe40351d84cfd6aaa0238f9a653d69aa1 (patch) | |
| tree | 651cac93d8fb2446d0cac5a2d4b60f9f8f23e7da /flash.h | |
| parent | b1f858f65b2abd276542650d8cb9e382da258967 (diff) | |
| download | flashrom-d3b6acffe40351d84cfd6aaa0238f9a653d69aa1.tar.gz flashrom-d3b6acffe40351d84cfd6aaa0238f9a653d69aa1.tar.bz2 flashrom-d3b6acffe40351d84cfd6aaa0238f9a653d69aa1.zip | |
Add writeprotect support infrastructure
The following just lays out the structure for write protect
manipulation of SPI flash chips in Flashrom. We later follow
up with adding support for each manufacturer group.
BUG=b:153800563
BRANCH=none
TEST=builds
Change-Id: Id93b5a1cb2da476fa8a7dde41d7b963024117474
Signed-off-by: Edward O'Callaghan <quasisec@google.com>
Reviewed-on: https://review.coreboot.org/c/flashrom/+/40325
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Diffstat (limited to 'flash.h')
| -rw-r--r-- | flash.h | 4 |
1 files changed, 4 insertions, 0 deletions
@@ -235,6 +235,8 @@ struct flashchip { int (*unlock) (struct flashctx *flash); int (*write) (struct flashctx *flash, const uint8_t *buf, unsigned int start, unsigned int len); int (*read) (struct flashctx *flash, uint8_t *buf, unsigned int start, unsigned int len); + uint8_t (*read_status) (const struct flashctx *flash); + int (*write_status) (const struct flashctx *flash, int status); struct voltage { uint16_t min; uint16_t max; @@ -243,6 +245,8 @@ struct flashchip { /* SPI specific options (TODO: Make it a union in case other bustypes get specific options.) */ uint8_t wrea_override; /**< override opcode for write extended address register */ + + struct wp *wp; }; struct flashrom_flashctx { |