spi25: Integrate 4BA support

Allow 4-byte addresses for instructions usually used with 3-byte
addresses. Decide in which way the 4th byte will be communicated
based on the state of the chip (i.e. have we enabled 4BA mode)
and a new feature bit for an extended address register. If we
are not in 4BA mode and no extended address register is available
or the write to it fails, bail out.

We cache the state of 4BA mode and the extended address register
in the flashctx.

Change-Id: I644600beaab9a571b97b67f7516abe571d3460c1
Signed-off-by: Nico Huber <nico.h@gmx.de>
Reviewed-on: https://review.coreboot.org/22384
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>

1 files changed, 8 insertions, 0 deletions

diff --git a/flash.h b/flash.h
index b18d698d8..5cb7040e9 100644
--- a/flash.h
+++ b/flash.h
@@ -120,6 +120,8 @@ enum write_granularity {
 #define FEATURE_OTP		(1 << 8)
 #define FEATURE_QPI		(1 << 9)
 #define FEATURE_4BA_SUPPORT	(1 << 10)
+#define FEATURE_4BA_EXT_ADDR	(1 << 11) /**< Regular 3-byte operations can be used by writing the most
+					       significant address byte into an extended address register. */
 
 enum test_state {
 	OK = 0,
@@ -236,6 +238,12 @@ struct flashrom_flashctx {
 		bool verify_after_write;
 		bool verify_whole_chip;
 	} flags;
+	/* We cache the state of the extended address register (highest byte
+           of a 4BA for 3BA instructions) and the state of the 4BA mode here.
+           If possible, we enter 4BA mode early. If that fails, we make use
+           of the extended address register. */
+	int address_high_byte;
+	bool in_4ba_mode;
 };
 
 /* Timing used in probe routines. ZERO is -2 to differentiate between an unset