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| author | Artur Kowalski <artur.kowalski@3mdeb.com> | 2022-10-19 16:37:10 +0200 |
|---|---|---|
| committer | Anastasia Klimchuk <aklm@chromium.org> | 2023-07-12 07:53:07 +0000 |
| commit | af8c203436567fe6ae65f1cb18c3b30bb0db7de5 (patch) | |
| tree | 5a40f4cab325320ceabb93fad360fb6880db14b6 /flashchips.c | |
| parent | aac723f18418418a804d8e2b93814a0b64d9d544 (diff) | |
| download | flashrom-af8c203436567fe6ae65f1cb18c3b30bb0db7de5.tar.gz flashrom-af8c203436567fe6ae65f1cb18c3b30bb0db7de5.tar.bz2 flashrom-af8c203436567fe6ae65f1cb18c3b30bb0db7de5.zip | |
flashchips: add support for MX77L25650F chip
Add initial support for Macronix MX77L25650F. Can read, write and erase
the chip.
Change-Id: Iaea5485f8b59b8538dc47beada2c308376ea027c
Signed-off-by: Artur Kowalski <artur.kowalski@3mdeb.com>
Signed-off-by: Sergii Dmytruk <sergii.dmytruk@3mdeb.com>
Signed-off-by: ServError <admin@serverror.com>
Reviewed-on: https://review.coreboot.org/c/flashrom/+/68557
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Anastasia Klimchuk <aklm@chromium.org>
Diffstat (limited to 'flashchips.c')
| -rw-r--r-- | flashchips.c | 40 |
1 files changed, 40 insertions, 0 deletions
diff --git a/flashchips.c b/flashchips.c index b11c558a0..d1ce20d14 100644 --- a/flashchips.c +++ b/flashchips.c @@ -10854,6 +10854,46 @@ const struct flashchip flashchips[] = { .voltage = {2700, 3600}, }, + { + .vendor = "Macronix", + .name = "MX77L25650F", + .bustype = BUS_SPI, + .manufacture_id = MACRONIX_ID, + .model_id = MACRONIX_MX77L25650F, + .total_size = 32768, + .page_size = 256, + /* OTP: 512B total; enter 0xB1, exit 0xC1 */ + .feature_bits = FEATURE_WRSR_WREN | FEATURE_OTP | FEATURE_4BA, + .tested = TEST_OK_PREW, + .probe = PROBE_SPI_RDID, + .probe_timing = TIMING_ZERO, + .block_erasers = + { + { + .eraseblocks = { {4 * 1024, 8192} }, + .block_erase = SPI_BLOCK_ERASE_20, + }, { + .eraseblocks = { {32 * 1024, 1024} }, + .block_erase = SPI_BLOCK_ERASE_52, + }, { + .eraseblocks = { {64 * 1024, 512} }, + .block_erase = SPI_BLOCK_ERASE_D8, + }, { + .eraseblocks = { {32 * 1024 * 1024, 1} }, + .block_erase = SPI_BLOCK_ERASE_60, + }, { + .eraseblocks = { {32 * 1024 * 1024, 1} }, + .block_erase = SPI_BLOCK_ERASE_C7, + } + }, + /* TODO: block WP, security register, configuration register */ + .printlock = SPI_PRETTYPRINT_STATUS_REGISTER_BP3_SRWD, /* bit6 is quad enable */ + .unlock = SPI_DISABLE_BLOCKPROTECT_BP3_SRWD, + .write = SPI_CHIP_WRITE256, + .read = SPI_CHIP_READ, /* Fast read (0x0B) supported */ + .voltage = {2700, 3600}, + }, + /* The ST M25P05 is a bit of a problem. It has the same ID as the * ST M25P05-A in RES mode, but supports only 128 byte writes instead * of 256 byte writes. We rely heavily on the fact that PROBE_SPI_RES1 |