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| author | Rick Altherr <kc8apf@kc8apf.net> | 2022-12-22 10:25:34 -0800 |
|---|---|---|
| committer | Anastasia Klimchuk <aklm@chromium.org> | 2023-01-15 10:28:19 +0000 |
| commit | d18c099cacca4f3d5635dd5df349efe8077c883e (patch) | |
| tree | c0e52fb2bec591b2a63fcb9cbfff82b1ba337338 /flashchips.c | |
| parent | 7440542ecbcb31cba33c0a2ef267c677b82d2426 (diff) | |
| download | flashrom-d18c099cacca4f3d5635dd5df349efe8077c883e.tar.gz flashrom-d18c099cacca4f3d5635dd5df349efe8077c883e.tar.bz2 flashrom-d18c099cacca4f3d5635dd5df349efe8077c883e.zip | |
flashchips: Remove FEATURE_4BA_WREN for MT25QL128 and mark as tested
Using both a Dediprog SF100 and a Bus Pirate, read and erase works
correctly on a MT25QL128 but writes were failing to take effect.
Currently, the entry in flashchips.c indicates that this device supports
4-byte addressing. Micron's datasheet indicates that it does not.
After removing FEATURE_4BA_WREN from feature_bits, both SF100 and
Bus Pirate were able to successfully read, erase, and write a
MT25QL128 so also marking as tested.
Change-Id: I6341456c722840a413bd2c51fe9a78bbda5cdbab
Signed-off-by: Rick Altherr <kc8apf@kc8apf.net>
Reviewed-on: https://review.coreboot.org/c/flashrom/+/71206
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-by: Anastasia Klimchuk <aklm@chromium.org>
Diffstat (limited to 'flashchips.c')
| -rw-r--r-- | flashchips.c | 4 |
1 files changed, 2 insertions, 2 deletions
diff --git a/flashchips.c b/flashchips.c index 9818eacaf..625fe6209 100644 --- a/flashchips.c +++ b/flashchips.c @@ -11997,8 +11997,8 @@ const struct flashchip flashchips[] = { .page_size = 256, /* supports SFDP */ /* OTP: 64B total; read 0x4B, write 0x42 */ - .feature_bits = FEATURE_WRSR_WREN | FEATURE_OTP | FEATURE_4BA_WREN, - .tested = TEST_UNTESTED, + .feature_bits = FEATURE_WRSR_WREN | FEATURE_OTP, + .tested = TEST_OK_PREW, .probe = PROBE_SPI_RDID, .probe_timing = TIMING_ZERO, .block_erasers = |