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| author | Sergii Dmytruk <sergii.dmytruk@3mdeb.com> | 2022-07-25 00:28:35 +0300 |
|---|---|---|
| committer | Anastasia Klimchuk <aklm@chromium.org> | 2022-11-19 07:14:25 +0000 |
| commit | f6b486da148654305fbc91503ffca2206fce8eec (patch) | |
| tree | 654da519ebe614cb927fde5305158db80dc1bbd0 /flashchips.c | |
| parent | 1428ca25d2473eb4e6368214f79eb1202d0caad5 (diff) | |
| download | flashrom-f6b486da148654305fbc91503ffca2206fce8eec.tar.gz flashrom-f6b486da148654305fbc91503ffca2206fce8eec.tar.bz2 flashrom-f6b486da148654305fbc91503ffca2206fce8eec.zip | |
flashchips.c: enable WP for MT25QL512, N25Q0{32,64}..{1,3}E
Change-Id: Ib0f3cb9516cea7bb678842a358a82099221e1ed9
Signed-off-by: Sergii Dmytruk <sergii.dmytruk@3mdeb.com>
Reviewed-on: https://review.coreboot.org/c/flashrom/+/66215
Reviewed-by: Anastasia Klimchuk <aklm@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Diffstat (limited to 'flashchips.c')
| -rw-r--r-- | flashchips.c | 51 |
1 files changed, 51 insertions, 0 deletions
diff --git a/flashchips.c b/flashchips.c index efe71d875..2f328bb7d 100644 --- a/flashchips.c +++ b/flashchips.c @@ -11258,6 +11258,17 @@ const struct flashchip flashchips[] = { .write = SPI_CHIP_WRITE256, /* Multi I/O supported */ .read = SPI_CHIP_READ, /* Fast read (0x0B) and multi I/O supported */ .voltage = {1700, 2000}, + .reg_bits = + { + /* + * There is also a volatile lock register per 64KiB sector, which is not + * mutually exclusive with BP-based protection. + */ + .srp = {STATUS1, 7, RW}, + .bp = {{STATUS1, 2, RW}, {STATUS1, 3, RW}, {STATUS1, 4, RW}}, + .tb = {STATUS1, 5, RW}, + }, + .decode_range = DECODE_RANGE_SPI25, }, { @@ -11292,6 +11303,17 @@ const struct flashchip flashchips[] = { .write = SPI_CHIP_WRITE256, /* Multi I/O supported */ .read = SPI_CHIP_READ, /* Fast read (0x0B) and multi I/O supported */ .voltage = {2700, 3600}, + .reg_bits = + { + /* + * There is also a volatile lock register per 64KiB sector, which is not + * mutually exclusive with BP-based protection. + */ + .srp = {STATUS1, 7, RW}, + .bp = {{STATUS1, 2, RW}, {STATUS1, 3, RW}, {STATUS1, 4, RW}}, + .tb = {STATUS1, 5, RW}, + }, + .decode_range = DECODE_RANGE_SPI25, }, { @@ -11326,6 +11348,17 @@ const struct flashchip flashchips[] = { .write = SPI_CHIP_WRITE256, /* Multi I/O supported */ .read = SPI_CHIP_READ, /* Fast read (0x0B) and multi I/O supported */ .voltage = {1700, 2000}, + .reg_bits = + { + /* + * There is also a volatile lock register per 64KiB sector, which is not + * mutually exclusive with BP-based protection. + */ + .srp = {STATUS1, 7, RW}, + .bp = {{STATUS1, 2, RW}, {STATUS1, 3, RW}, {STATUS1, 4, RW}, {STATUS1, 6, RW}}, + .tb = {STATUS1, 5, RW}, + }, + .decode_range = DECODE_RANGE_SPI25, }, { @@ -11360,6 +11393,17 @@ const struct flashchip flashchips[] = { .write = SPI_CHIP_WRITE256, /* Multi I/O supported */ .read = SPI_CHIP_READ, /* Fast read (0x0B) and multi I/O supported */ .voltage = {2700, 3600}, + .reg_bits = + { + /* + * There is also a volatile lock register per 64KiB sector, which is not + * mutually exclusive with BP-based protection. + */ + .srp = {STATUS1, 7, RW}, + .bp = {{STATUS1, 2, RW}, {STATUS1, 3, RW}, {STATUS1, 4, RW}, {STATUS1, 6, RW}}, + .tb = {STATUS1, 5, RW}, + }, + .decode_range = DECODE_RANGE_SPI25, }, { @@ -11999,6 +12043,13 @@ const struct flashchip flashchips[] = { .write = SPI_CHIP_WRITE256, /* Multi I/O supported */ .read = SPI_CHIP_READ, /* Fast read (0x0B) and multi I/O supported */ .voltage = {2700, 3600}, + .reg_bits = + { + .srp = {STATUS1, 7, RW}, + .bp = {{STATUS1, 2, RW}, {STATUS1, 3, RW}, {STATUS1, 4, RW}, {STATUS1, 6, RW}}, + .tb = {STATUS1, 5, RW}, + }, + .decode_range = DECODE_RANGE_SPI25, }, { |