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authorCarl-Daniel Hailfinger <c-d.hailfinger.devel.2006@gmx.net>2020-01-20 11:22:41 +0100
committerCarl-Daniel Hailfinger <c-d.hailfinger.devel.2006@gmx.net>2020-01-20 13:02:48 +0000
commite4c2b48f39902c7ff49a6a9e29525bdd3092c412 (patch)
tree58008ef76cc0d8540ab5bf4cce80973e9fa05a59 /flashchips.h
parent67710afe4e34f63a6e7b28d5493753caa8e79a52 (diff)
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Fix typos
Signed-off-by: Carl-Daniel Hailfinger <c-d.hailfinger.devel.2006@gmx.net> Change-Id: Ia5ed00c488b0719b2bdd6c8f304900511684f445 Reviewed-on: https://review.coreboot.org/c/flashrom/+/38477 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-by: Nico Huber <nico.h@gmx.de>
Diffstat (limited to 'flashchips.h')
-rw-r--r--flashchips.h2
1 files changed, 1 insertions, 1 deletions
diff --git a/flashchips.h b/flashchips.h
index f02958c2a..14ab6de94 100644
--- a/flashchips.h
+++ b/flashchips.h
@@ -602,7 +602,7 @@
#define PMC_PM49FL004 0x6E
/*
- * The Sanyo chip found so far uses SPI, first byte is manufacture code,
+ * The Sanyo chip found so far uses SPI, first byte is manufacturer code,
* second byte is the device code,
* third byte is a dummy byte.
*/