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| author | Rob Barnes <robbarnes@google.com> | 2020-01-21 09:10:51 -0700 |
|---|---|---|
| committer | Edward O'Callaghan <quasisec@chromium.org> | 2020-03-03 13:01:54 +0000 |
| commit | 703de983d8ccdb94232bf30cc6e64389741a0fef (patch) | |
| tree | 1daf721a0ff04842665a8038b40c0ac8a7e9be0a /flashrom.8.tmpl | |
| parent | ad08aef69c84fbd23ce680c91de954aaae7d3fb4 (diff) | |
| download | flashrom-703de983d8ccdb94232bf30cc6e64389741a0fef.tar.gz flashrom-703de983d8ccdb94232bf30cc6e64389741a0fef.tar.bz2 flashrom-703de983d8ccdb94232bf30cc6e64389741a0fef.zip | |
sb600spi: Add spireadmode
Added spireadmode for >= Bolton.
Do not override speed or read mode for >= Bolton if parameter not
specified.
Minor cleanup of sb600spi.c code.
TEST=Manual: deploy on tremblye read flash using various parameters
BUG=b:147665085,b:147666328
BRANCH=master
Change-Id: Id7fec7eb87ff811148217dc56a86dca3fef122ff
Signed-off-by: Rob Barnes <robbarnes@google.com>
Reviewed-on: https://review.coreboot.org/c/flashrom/+/38833
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Edward O'Callaghan <quasisec@chromium.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Diffstat (limited to 'flashrom.8.tmpl')
| -rw-r--r-- | flashrom.8.tmpl | 20 |
1 files changed, 19 insertions, 1 deletions
diff --git a/flashrom.8.tmpl b/flashrom.8.tmpl index aa5bcd457..fde98c04c 100644 --- a/flashrom.8.tmpl +++ b/flashrom.8.tmpl @@ -497,11 +497,29 @@ Support of individual frequencies depends on the generation of the chipset: .sp * SB6xx, SB7xx, SP5xxx: from 16.5 MHz up to and including 33 MHz .sp +-The default is to use 16.5 MHz and disable Fast Reads. +.sp * SB8xx, SB9xx, Hudson: from 16.5 MHz up to and including 66 MHz .sp +-The default is to use 16.5 MHz and disable Fast Reads. +.sp * Yangtze (with SPI 100 engine as found in Kabini and Tamesh): all of them .sp -The default is to use 16.5 MHz and disable Fast Reads. +-The default is to use the frequency that is currently configured. +.sp +An optional +.B spireadmode +parameter specifies the read mode of the SPI bus where applicable (Bolton or later). +Syntax is +.sp +.B " flashrom \-p internal:spireadmode=mode" +.sp +where +.B mode +can be +.BR "'Normal\ (up\ to\ 33 MHz)'" ", " "'Normal\ (up\ to\ 66 MHz)'" ", " "'Dual\ IO\ (1-1-2)'" ", " "'Quad\ IO\ (1-1-4)'" ", " "'Dual\ IO\ (1-2-2)'" ", " "'Quad\ IO\ (1-4-4)'" ", or " "'Fast\ Read'" "." +.sp +The default is to use the read mode that is currently configured. .TP .B Intel chipsets .sp |