summaryrefslogtreecommitdiffstats
path: root/ft2232_spi.c
diff options
context:
space:
mode:
authorsibradzic <5964548+sibradzic@users.noreply.github.com>2020-02-04 18:24:58 +0900
committerEdward O'Callaghan <quasisec@chromium.org>2020-03-09 04:54:49 +0000
commitba6575de82f091b97ea0f2efcf2f79ef3739d64f (patch)
tree67a95754a689c50c322e90796cb8cde675ac692f /ft2232_spi.c
parent703de983d8ccdb94232bf30cc6e64389741a0fef (diff)
downloadflashrom-ba6575de82f091b97ea0f2efcf2f79ef3739d64f.tar.gz
flashrom-ba6575de82f091b97ea0f2efcf2f79ef3739d64f.tar.bz2
flashrom-ba6575de82f091b97ea0f2efcf2f79ef3739d64f.zip
ft2232_spi: Enhance csgpiol parameter for FT2232
This allows multiple 'csgpiol' bits to be set to active state at the same time. Previously, only one GPIOL could be activated. I have an use-case such that FT4232H is wired to two different SPI chips, and in order to select one of them two GPIOLs have to be set. Now, one can enable any particular GPIOL, for example: csgpiol=01 would activate GPIOL0 and GPIOL1 at the same time. The change is backward-compatible with previous csgpiol formatting. Signed-off-by: Samir Ibradzic <sibradzic@gmail.com> Change-Id: I645ddaa9852e9995bd2a6764862fda2b2ef0c26b Reviewed-on: https://review.coreboot.org/c/flashrom/+/38705 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Diffstat (limited to 'ft2232_spi.c')
-rw-r--r--ft2232_spi.c40
1 files changed, 26 insertions, 14 deletions
diff --git a/ft2232_spi.c b/ft2232_spi.c
index 5bdc2a7b2..3e4dc9e44 100644
--- a/ft2232_spi.c
+++ b/ft2232_spi.c
@@ -86,10 +86,17 @@ const struct dev_entry devs_ft2232spi[] = {
/* The variables cs_bits and pindir store the values for the "set data bits low byte" MPSSE command that
* sets the initial state and the direction of the I/O pins. The pin offsets are as follows:
- * SCK is bit 0.
- * DO is bit 1.
- * DI is bit 2.
- * CS is bit 3.
+ * TCK/SK is bit 0.
+ * TDI/DO is bit 1.
+ * TDO/DI is bit 2.
+ * TMS/CS is bit 3.
+ * GPIOL0 is bit 4.
+ * GPIOL1 is bit 5.
+ * GPIOL2 is bit 6.
+ * GPIOL3 is bit 7.
+ *
+ * The pin signal direction bit offsets follow the same order; 0 means that
+ * pin at the matching bit index is an input, 1 means pin is an output.
*
* The default values (set below) are used for most devices:
* value: 0x08 CS=high, DI=low, DO=low, SK=low
@@ -331,19 +338,24 @@ int ft2232_spi_init(void)
}
free(arg);
+ /* Allows setting multiple GPIOL states, for example: csgpiol=012 */
arg = extract_programmer_param("csgpiol");
if (arg) {
- char *endptr;
- unsigned int temp = strtoul(arg, &endptr, 10);
- if (*endptr || endptr == arg || temp > 3) {
- msg_perr("Error: Invalid GPIOL specified: \"%s\".\n"
- "Valid values are between 0 and 3.\n", arg);
- free(arg);
- return -2;
+ unsigned int ngpios = strlen(arg);
+ for (unsigned int i = 0; i <= ngpios; i++) {
+ int temp = arg[i] - '0';
+ if (ngpios == 0 || (ngpios != i && (temp < 0 || temp > 3))) {
+ msg_perr("Error: Invalid GPIOLs specified: \"%s\".\n"
+ "Valid values are numbers between 0 and 3. "
+ "Multiple GPIOLs can be specified.\n", arg);
+ free(arg);
+ return -2;
+ } else {
+ unsigned int pin = temp + 4;
+ cs_bits |= 1 << pin;
+ pindir |= 1 << pin;
+ }
}
- unsigned int pin = temp + 4;
- cs_bits |= 1 << pin;
- pindir |= 1 << pin;
}
free(arg);