Add Tiger Lake U Premium support

Tiger Lake has very low ICCRIBA (TGL=0x11, CNL=0x34 and CML=0x34) and
detects as unknown chipset compatible with 300 series chipset. Add a
new enum CHIPSET_500_SERIES_TIGER_POINT and treat it identically to
CHIPSET_400_SERIES_COMET_POINT. There are some exceptions though,
ICCRIBA is no longer present n descriptor content so a new union has
been defined for new fields and used in descriptor guessing.
freq_read field is not present on Tiger Lake, moreover in CannonPoint
and Comet Point this field is used as eSPI/EC frequency, so a new
function to print read frequency has ben added. Finally Tiger lake
boot straps include eSPI, so a new bus has been added for the new
straps.

TEST=Flash BIOS region on Intel i5-1135G7

Signed-off-by: Michał Żygowski <michal.zygowski@3mdeb.com>
Change-Id: I28f3b6fe9f8ce9e976a6808683f46b6f4ec72bdd
Reviewed-on: https://review.coreboot.org/c/flashrom/+/55578
Reviewed-by: Nico Huber <nico.h@gmx.de>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>

1 files changed, 7 insertions, 0 deletions

diff --git a/ich_descriptors.h b/ich_descriptors.h
index d00af63f3..cd5a45cb1 100644
--- a/ich_descriptors.h
+++ b/ich_descriptors.h
@@ -95,6 +95,13 @@ struct ich_desc_content {
 				 ICCRIBA	:8, /* ICC Reg. Init Base Addr.	(new since Sandy Bridge) */
 				 RIL		:8; /* Register Init Length	(new since Hawell) */
 		};
+		struct {	/* new since Tiger Point */
+			uint32_t		:2,
+				 CSSO		:10, /* CPU Soft Strap Offset from PMC Base */
+						:4,
+				 CSSL		:8,  /* CPU Soft Strap Length */
+						:8;
+		};
 	};
 };