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| author | Edward O'Callaghan <quasisec@google.com> | 2022-10-17 12:31:59 +1100 |
|---|---|---|
| committer | Edward O'Callaghan <quasisec@chromium.org> | 2022-12-12 00:02:26 +0000 |
| commit | 1e01eefcba573c436d55b863c7972b3029564215 (patch) | |
| tree | aa8850783eb557f4921020e8171fbd7c3ea1ade3 /ichspi.c | |
| parent | 78e421bdf73d5739daa25a9f71b2c323dc98e840 (diff) | |
| download | flashrom-1e01eefcba573c436d55b863c7972b3029564215.tar.gz flashrom-1e01eefcba573c436d55b863c7972b3029564215.tar.bz2 flashrom-1e01eefcba573c436d55b863c7972b3029564215.zip | |
tree/: Replace NULL-case of programmer_delay() with internal_delay
Replace `programmer_delay(NULL, [..])` calls with direct
`internal_delay([..])` dispatches explicitly. Custom driver
delays remain hooked as well as core flashrom logic. The
NULL base case of 'programmer_delay()' then becomes a condition
to validate for layering violations or invalid flash contexts.
Change-Id: I1da230804d5e8f47a6e281feb66f381514dc6861
Signed-off-by: Edward O'Callaghan <quasisec@google.com>
Reviewed-on: https://review.coreboot.org/c/flashrom/+/68434
Reviewed-by: Anastasia Klimchuk <aklm@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Diffstat (limited to 'ichspi.c')
| -rw-r--r-- | ichspi.c | 10 |
1 files changed, 5 insertions, 5 deletions
@@ -875,7 +875,7 @@ static int ich7_run_opcode(OPCODE op, uint32_t offset, timeout = 100 * 60; /* 60 ms are 9.6 million cycles at 16 MHz. */ while ((REGREAD16(ICH7_REG_SPIS) & SPIS_SCIP) && --timeout) { - programmer_delay(NULL, 10); + internal_delay(10); } if (!timeout) { msg_perr("Error: SCIP never cleared!\n"); @@ -951,7 +951,7 @@ static int ich7_run_opcode(OPCODE op, uint32_t offset, /* Wait for Cycle Done Status or Flash Cycle Error. */ while (((REGREAD16(ICH7_REG_SPIS) & (SPIS_CDS | SPIS_FCERR)) == 0) && --timeout) { - programmer_delay(NULL, 10); + internal_delay(10); } if (!timeout) { msg_perr("timeout, ICH7_REG_SPIS=0x%04x\n", REGREAD16(ICH7_REG_SPIS)); @@ -991,7 +991,7 @@ static int ich9_run_opcode(OPCODE op, uint32_t offset, timeout = 100 * 60; /* 60 ms are 9.6 million cycles at 16 MHz. */ while ((REGREAD8(swseq_data.reg_ssfsc) & SSFS_SCIP) && --timeout) { - programmer_delay(NULL, 10); + internal_delay(10); } if (!timeout) { msg_perr("Error: SCIP never cleared!\n"); @@ -1071,7 +1071,7 @@ static int ich9_run_opcode(OPCODE op, uint32_t offset, /* Wait for Cycle Done Status or Flash Cycle Error. */ while (((REGREAD32(swseq_data.reg_ssfsc) & (SSFS_FDONE | SSFS_FCERR)) == 0) && --timeout) { - programmer_delay(NULL, 10); + internal_delay(10); } if (!timeout) { msg_perr("timeout, REG_SSFS=0x%08x\n", REGREAD32(swseq_data.reg_ssfsc)); @@ -1319,7 +1319,7 @@ static int ich_hwseq_wait_for_cycle_complete(unsigned int len, enum ich_chipset while ((((hsfs = REGREAD16(ICH9_REG_HSFS)) & (HSFS_FDONE | HSFS_FCERR)) == 0) && --timeout_us) { - programmer_delay(NULL, 8); + internal_delay(8); } REGWRITE16(ICH9_REG_HSFS, REGREAD16(ICH9_REG_HSFS)); if (!timeout_us) { |