diff options
| author | Edward O'Callaghan <quasisec@google.com> | 2022-06-17 21:59:45 +1000 |
|---|---|---|
| committer | Edward O'Callaghan <quasisec@chromium.org> | 2022-08-15 12:45:59 +0000 |
| commit | 6a3988b6cd75f6eb1e987add17c680d15f2cfdfc (patch) | |
| tree | d75434fb32b39151940802aef923148e951aa460 /ichspi.c | |
| parent | 456be2ad7af086c52e86a698b0d463e3f1589027 (diff) | |
| download | flashrom-6a3988b6cd75f6eb1e987add17c680d15f2cfdfc.tar.gz flashrom-6a3988b6cd75f6eb1e987add17c680d15f2cfdfc.tar.bz2 flashrom-6a3988b6cd75f6eb1e987add17c680d15f2cfdfc.zip | |
ichspi.c: Make ich_hwseq_wait_for_cycle_complete() take addr_mask as arg
Move towards functions depending less on globals.
BUG=b:237839418
TEST=builds
Change-Id: I7c02a33c0984f24efcaff967c496880d70922575
Signed-off-by: Edward O'Callaghan <quasisec@google.com>
Reviewed-on: https://review.coreboot.org/c/flashrom/+/65204
Reviewed-by: Alexander Goncharov <chat@joursoir.net>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Anastasia Klimchuk <aklm@chromium.org>
Reviewed-by: Thomas Heijligen <src@posteo.de>
Diffstat (limited to 'ichspi.c')
| -rw-r--r-- | ichspi.c | 16 |
1 files changed, 8 insertions, 8 deletions
@@ -1299,7 +1299,7 @@ static uint32_t ich_hwseq_get_erase_block_size(unsigned int addr, uint32_t addr_ Resets all error flags in HSFS. Returns 0 if the cycle completes successfully without errors within timeout us, 1 on errors. */ -static int ich_hwseq_wait_for_cycle_complete(unsigned int len, enum ich_chipset ich_gen) +static int ich_hwseq_wait_for_cycle_complete(unsigned int len, enum ich_chipset ich_gen, uint32_t addr_mask) { /* * The SPI bus may be busy due to performing operations from other masters, hence @@ -1317,7 +1317,7 @@ static int ich_hwseq_wait_for_cycle_complete(unsigned int len, enum ich_chipset } REGWRITE16(ICH9_REG_HSFS, REGREAD16(ICH9_REG_HSFS)); if (!timeout_us) { - addr = REGREAD32(ICH9_REG_FADDR) & hwseq_data.addr_mask; + addr = REGREAD32(ICH9_REG_FADDR) & addr_mask; msg_perr("Timeout error between offset 0x%08x and " "0x%08x (= 0x%08x + %d)!\n", addr, addr + len - 1, addr, len - 1); @@ -1327,7 +1327,7 @@ static int ich_hwseq_wait_for_cycle_complete(unsigned int len, enum ich_chipset } if (hsfs & HSFS_FCERR) { - addr = REGREAD32(ICH9_REG_FADDR) & hwseq_data.addr_mask; + addr = REGREAD32(ICH9_REG_FADDR) & addr_mask; msg_perr("Transaction error between offset 0x%08x and " "0x%08x (= 0x%08x + %d)!\n", addr, addr + len - 1, addr, len - 1); @@ -1365,7 +1365,7 @@ static int ich_hwseq_read_status(const struct flashctx *flash, enum flash_reg re hsfc |= HSFC_FGO; /* start */ REGWRITE16(ICH9_REG_HSFC, hsfc); - if (ich_hwseq_wait_for_cycle_complete(len, ich_generation)) { + if (ich_hwseq_wait_for_cycle_complete(len, ich_generation, hwseq_data.addr_mask)) { msg_perr("Reading Status register failed\n!!"); return -1; } @@ -1402,7 +1402,7 @@ static int ich_hwseq_write_status(const struct flashctx *flash, enum flash_reg r hsfc |= HSFC_FGO; /* start */ REGWRITE16(ICH9_REG_HSFC, hsfc); - if (ich_hwseq_wait_for_cycle_complete(len, ich_generation)) { + if (ich_hwseq_wait_for_cycle_complete(len, ich_generation, hwseq_data.addr_mask)) { msg_perr("Writing Status register failed\n!!"); return -1; } @@ -1513,7 +1513,7 @@ static int ich_hwseq_block_erase(struct flashctx *flash, unsigned int addr, prettyprint_ich9_reg_hsfc(hsfc, ich_generation); REGWRITE16(ICH9_REG_HSFC, hsfc); - if (ich_hwseq_wait_for_cycle_complete(len, ich_generation)) + if (ich_hwseq_wait_for_cycle_complete(len, ich_generation, hwseq_data.addr_mask)) return -1; return 0; } @@ -1556,7 +1556,7 @@ static int ich_hwseq_read(struct flashctx *flash, uint8_t *buf, hsfc |= HSFC_FGO; /* start */ REGWRITE16(ICH9_REG_HSFC, hsfc); - if (ich_hwseq_wait_for_cycle_complete(block_len, ich_generation)) + if (ich_hwseq_wait_for_cycle_complete(block_len, ich_generation, hwseq_data.addr_mask)) return 1; ich_read_data(buf, block_len, ICH9_REG_FDATA0); addr += block_len; @@ -1603,7 +1603,7 @@ static int ich_hwseq_write(struct flashctx *flash, const uint8_t *buf, unsigned hsfc |= HSFC_FGO; /* start */ REGWRITE16(ICH9_REG_HSFC, hsfc); - if (ich_hwseq_wait_for_cycle_complete(block_len, ich_generation)) + if (ich_hwseq_wait_for_cycle_complete(block_len, ich_generation, hwseq_data.addr_mask)) return -1; addr += block_len; buf += block_len; |