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author | Helge Wagner <helge.wagner@ge.com> | 2010-08-11 21:06:10 +0000 |
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committer | Michael Karcher <flashrom@mkarcher.dialup.fu-berlin.de> | 2010-08-11 21:06:10 +0000 |
commit | a319be14d4e6b9a8f01359fb3575a02d80014f66 (patch) | |
tree | d1efc68bded2398bfbea81766793bc4853261c6a /ichspi.c | |
parent | d9f266d1fb83fb0f5bffe470633a7127c23cee91 (diff) | |
download | flashrom-a319be14d4e6b9a8f01359fb3575a02d80014f66.tar.gz flashrom-a319be14d4e6b9a8f01359fb3575a02d80014f66.tar.bz2 flashrom-a319be14d4e6b9a8f01359fb3575a02d80014f66.zip |
Add support for Intel 5 Series / 3400 Series chipsets
(At least) for the QM57 which i have tested an additional patch was
needed as some reserved bits in the "Software Sequencing Flash Control
Register" (SSFC) needs to be programmed to 1 in the QM57.
Corresponding to flashrom svn r1137.
Signed-off-by: Helge Wagner <helge.wagner@ge.com>
Acked-by: Michael Karcher <flashrom@mkarcher.dialup.fu-berlin.de>
Diffstat (limited to 'ichspi.c')
-rw-r--r-- | ichspi.c | 4 |
1 files changed, 3 insertions, 1 deletions
@@ -560,7 +560,9 @@ static int ich9_run_opcode(OPCODE op, uint32_t offset, } /* Assemble SSFS + SSFC */ - temp32 = 0; + /* keep reserved bits (23-19,7,0) */ + temp32 = REGREAD32(ICH9_REG_SSFS); + temp32 &= 0xF8008100; /* clear error status registers */ temp32 |= (SSFS_CDS + SSFS_FCERR); |