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author | Anastasia Klimchuk <aklm@chromium.org> | 2022-11-21 12:50:07 +1100 |
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committer | Anastasia Klimchuk <aklm@chromium.org> | 2022-11-25 03:24:59 +0000 |
commit | f206183eb4eaa340deba83afde3d0110f3afad6e (patch) | |
tree | 2365c456b468acbaa361e2af537580e81ce53f67 /ichspi.c | |
parent | 8528ea0845171a4b26de44757d5b30c9727e8d5b (diff) | |
download | flashrom-f206183eb4eaa340deba83afde3d0110f3afad6e.tar.gz flashrom-f206183eb4eaa340deba83afde3d0110f3afad6e.tar.bz2 flashrom-f206183eb4eaa340deba83afde3d0110f3afad6e.zip |
opaque_master: Mark Opaque chip as tested for WP
Opaque masters, by design, populate the flashchip structure during
the execution of their probe function. Therefore any opaque master
operation displays a message to the user:
"This flash part has status UNTESTED for operations: WP".
However, for all the other operations (read, write, erase) opaque
masters always mark them as tested. Thus, align WP as marked tested
inline with other opaque chip operations.
BUG=b:258755442
TEST=the following does not display untested message:
1) flashrom -p dummy:size=8388608,emulate=VARIABLE_SIZE
2) flashrom -p internal (on Intel device)
Change-Id: I5ae4cb49eb0abc6ab26cfe2f3359e4e50dd4fd4f
Signed-off-by: Anastasia Klimchuk <aklm@chromium.org>
Reviewed-on: https://review.coreboot.org/c/flashrom/+/69842
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Edward O'Callaghan <quasisec@chromium.org>
Reviewed-by: Sergii Dmytruk <sergii.dmytruk@3mdeb.com>
Reviewed-by: Felix Singer <felixsinger@posteo.net>
Diffstat (limited to 'ichspi.c')
-rw-r--r-- | ichspi.c | 2 |
1 files changed, 1 insertions, 1 deletions
@@ -1485,7 +1485,7 @@ static int ich_hwseq_probe(struct flashctx *flash) msg_cdbg("In that range are %d erase blocks with %d B each.\n", size_high / erase_size_high, erase_size_high); } - flash->chip->tested = TEST_OK_PREW; + flash->chip->tested = TEST_OK_PREWB; return 1; } |