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| author | Edward O'Callaghan <quasisec@google.com> | 2022-05-16 15:38:18 +1000 |
|---|---|---|
| committer | Edward O'Callaghan <quasisec@chromium.org> | 2022-06-21 03:38:49 +0000 |
| commit | f630a1623f84b452873e3fc69d608925d90fd85b (patch) | |
| tree | 3656eb2d97bc0d869d0e6cb50abe3baa643beb7c /ichspi.c | |
| parent | fac9fc28f5a6cadf7c94264f429faa597a2058ac (diff) | |
| download | flashrom-f630a1623f84b452873e3fc69d608925d90fd85b.tar.gz flashrom-f630a1623f84b452873e3fc69d608925d90fd85b.tar.bz2 flashrom-f630a1623f84b452873e3fc69d608925d90fd85b.zip | |
writeprotect.c: Allow opaque masters to hook {read,write}_register()
Allow specialisation in opaque masters, such as ichspi hwseq, to
write to status registers.
Also update the dispatch logic in libflashrom to call wp code when
status register access functions are provided by an opaque master.
BUG=none
BRANCH=none
TEST=flashrom --wp-status on AMD and Intel DUTs
Change-Id: I3ab0d7f5f48338c8ecb118a69651c203fbc516ac
Signed-off-by: Edward O'Callaghan <quasisec@google.com>
Signed-off-by: Nikolai Artemiev <nartemiev@google.com>
Co-Authored-by: Nikolai Artemiev <nartemiev@google.com>
Reviewed-on: https://review.coreboot.org/c/flashrom/+/64375
Reviewed-by: Anastasia Klimchuk <aklm@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Diffstat (limited to 'ichspi.c')
0 files changed, 0 insertions, 0 deletions