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| author | Nico Huber <nico.h@gmx.de> | 2022-05-28 16:48:26 +0200 |
|---|---|---|
| committer | Nico Huber <nico.h@gmx.de> | 2022-06-20 16:36:20 +0000 |
| commit | f6d702e2d09f604830070fc0079374955481be5d (patch) | |
| tree | 506d2cccec587cc64278e956c554fb9201bf324a /include/spi.h | |
| parent | 7db2baa77d41c3a74449a3f2b907025f69b776b9 (diff) | |
| download | flashrom-f6d702e2d09f604830070fc0079374955481be5d.tar.gz flashrom-f6d702e2d09f604830070fc0079374955481be5d.tar.bz2 flashrom-f6d702e2d09f604830070fc0079374955481be5d.zip | |
spi25_statusreg: Allow WRSR_EXT for Status Register 3
Spansion flash chips S25FL128L and S25FL256L use the WRSR instruction to
write more than 2 registers. So align SR2 and SR3 support: The current
FEATURE_WRSR_EXT is renamed to FEATURE_WRSR_EXT2 and FEATURE_WRSR_EXT3
is added. Also, WRSR3 needs a separate flag now.
Verified that FEATURE_WRSR_EXT2 still works using the `dummy_flasher`.
Signed-off-by: Nico Huber <nico.h@gmx.de>
Change-Id: Ibdfc6eb3d2cfecbf8da0493d067031ddb079a094
Reviewed-on: https://review.coreboot.org/c/flashrom/+/64746
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Nikolai Artemiev <nartemiev@google.com>
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-by: Thomas Heijligen <src@posteo.de>
Diffstat (limited to 'include/spi.h')
| -rw-r--r-- | include/spi.h | 1 |
1 files changed, 0 insertions, 1 deletions
diff --git a/include/spi.h b/include/spi.h index 14f71aa06..05d2239a4 100644 --- a/include/spi.h +++ b/include/spi.h @@ -156,7 +156,6 @@ #define JEDEC_WRSR 0x01 #define JEDEC_WRSR_OUTSIZE 0x02 #define JEDEC_WRSR_INSIZE 0x00 -#define JEDEC_WRSR_EXT_OUTSIZE 0x03 /* Write Status Register 2 */ #define JEDEC_WRSR2 0x31 |