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authorEdward O'Callaghan <quasisec@google.com>2022-08-12 14:13:01 +1000
committerAnastasia Klimchuk <aklm@chromium.org>2022-09-07 01:53:16 +0000
commit848825e049dfa8e18e33ed9cfa3b4ea61ac6ee4a (patch)
treeba80059e530a825d8eb54c708c5369d18ceda085 /internal.c
parent1233e638336f2d67be57b31bb769aa85aa5bd583 (diff)
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it87spi.c: Allow passing programmer_cfg directly
Modify the type signature of the programmer entry-point xxx_init() functions to allow for the consumption of the programmer parameterisation string data. Change-Id: I598b1811c9734f41eee205d5a2b51ad8ac79e3ab Signed-off-by: Edward O'Callaghan <quasisec@google.com> Reviewed-on: https://review.coreboot.org/c/flashrom/+/66662 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Felix Singer <felixsinger@posteo.net> Reviewed-by: Anastasia Klimchuk <aklm@chromium.org>
Diffstat (limited to 'internal.c')
-rw-r--r--internal.c2
1 files changed, 1 insertions, 1 deletions
diff --git a/internal.c b/internal.c
index 66eebdc96..8b97f53d2 100644
--- a/internal.c
+++ b/internal.c
@@ -293,7 +293,7 @@ static int internal_init(const struct programmer_cfg *cfg)
#if defined(__i386__) || defined(__x86_64__)
/* Probe unconditionally for ITE Super I/O chips. This enables LPC->SPI translation on IT87* and
* parallel writes on IT8705F. Also, this handles the manual chip select for Gigabyte's DualBIOS. */
- init_superio_ite();
+ init_superio_ite(cfg);
if (board_flash_enable(board_vendor, board_model, cb_vendor, cb_model)) {
msg_perr("Aborting to be safe.\n");