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authorEdward O'Callaghan <quasisec@google.com>2022-08-12 14:13:01 +1000
committerAnastasia Klimchuk <aklm@chromium.org>2022-09-07 01:53:16 +0000
commit848825e049dfa8e18e33ed9cfa3b4ea61ac6ee4a (patch)
treeba80059e530a825d8eb54c708c5369d18ceda085 /it87spi.c
parent1233e638336f2d67be57b31bb769aa85aa5bd583 (diff)
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it87spi.c: Allow passing programmer_cfg directly
Modify the type signature of the programmer entry-point xxx_init() functions to allow for the consumption of the programmer parameterisation string data. Change-Id: I598b1811c9734f41eee205d5a2b51ad8ac79e3ab Signed-off-by: Edward O'Callaghan <quasisec@google.com> Reviewed-on: https://review.coreboot.org/c/flashrom/+/66662 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Felix Singer <felixsinger@posteo.net> Reviewed-by: Anastasia Klimchuk <aklm@chromium.org>
Diffstat (limited to 'it87spi.c')
-rw-r--r--it87spi.c6
1 files changed, 3 insertions, 3 deletions
diff --git a/it87spi.c b/it87spi.c
index 568d71432..bef60cbba 100644
--- a/it87spi.c
+++ b/it87spi.c
@@ -321,7 +321,7 @@ static const struct spi_master spi_master_it87xx = {
.probe_opcode = default_spi_probe_opcode,
};
-static uint16_t it87spi_probe(uint16_t port)
+static uint16_t it87spi_probe(const struct programmer_cfg *cfg, uint16_t port)
{
uint8_t tmp = 0;
uint16_t flashport = 0;
@@ -440,7 +440,7 @@ static uint16_t it87spi_probe(uint16_t port)
return register_spi_master(&spi_master_it87xx, data);
}
-int init_superio_ite(void)
+int init_superio_ite(const struct programmer_cfg *cfg)
{
int i;
int ret = 0;
@@ -458,7 +458,7 @@ int init_superio_ite(void)
case 0x8718:
case 0x8720:
case 0x8728:
- ret |= it87spi_probe(superios[i].port);
+ ret |= it87spi_probe(cfg, superios[i].port);
break;
default:
msg_pdbg2("Super I/O ID 0x%04hx is not on the list of flash-capable controllers.\n",