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| author | Edward O'Callaghan <quasisec@google.com> | 2022-10-26 13:46:14 +1100 |
|---|---|---|
| committer | Edward O'Callaghan <quasisec@chromium.org> | 2022-12-12 23:00:58 +0000 |
| commit | 76f28a3fc29b96c1c8cc76cba1279f92d2edc86e (patch) | |
| tree | 5f25bc8d28de469867e00b84c9d2026036eb9d9d /nicintel_eeprom.c | |
| parent | d1212796abc68ff480ff862d1a09ec3a1942fe97 (diff) | |
| download | flashrom-76f28a3fc29b96c1c8cc76cba1279f92d2edc86e.tar.gz flashrom-76f28a3fc29b96c1c8cc76cba1279f92d2edc86e.tar.bz2 flashrom-76f28a3fc29b96c1c8cc76cba1279f92d2edc86e.zip | |
tree/: Rename 'internal_delay()' to 'default_delay()'
The non-custom driver programmer delay implementation
'internal_delay()' is unrelated specifically to the
'internal' programmer. The delay implementation is
simply a platform-agnostic host delay implementation.
Therefore, rename to simply default_delay().
Change-Id: I5e04adf16812ceb1480992c92bca25ed80f8897a
Signed-off-by: Edward O'Callaghan <quasisec@google.com>
Reviewed-on: https://review.coreboot.org/c/flashrom/+/68855
Reviewed-by: Alexander Goncharov <chat@joursoir.net>
Reviewed-by: Felix Singer <felixsinger@posteo.net>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Diffstat (limited to 'nicintel_eeprom.c')
| -rw-r--r-- | nicintel_eeprom.c | 8 |
1 files changed, 4 insertions, 4 deletions
diff --git a/nicintel_eeprom.c b/nicintel_eeprom.c index 6922fb752..80ccd8878 100644 --- a/nicintel_eeprom.c +++ b/nicintel_eeprom.c @@ -213,7 +213,7 @@ static int nicintel_ee_write_word_i210(uint8_t *eebar, unsigned int addr, uint16 eewr |= BIT(EEWR_CMDV); pci_mmio_writel(eewr, eebar + EEWR); - internal_delay(5); + default_delay(5); int i; for (i = 0; i < MAX_ATTEMPTS; i++) if (pci_mmio_readl(eebar + EEWR) & BIT(EEWR_DONE)) @@ -338,7 +338,7 @@ static int nicintel_ee_ready(uint8_t *eebar) nicintel_ee_bitbang(eebar, 0x00, &rdsr); nicintel_ee_bitset(eebar, EEC, EE_CS, 1); - internal_delay(1); + default_delay(1); if (!(rdsr & SPI_SR_WIP)) { return 0; } @@ -379,7 +379,7 @@ static int nicintel_ee_write_82580(struct flashctx *flash, const uint8_t *buf, u nicintel_ee_bitset(eebar, EEC, EE_CS, 0); nicintel_ee_bitbang(eebar, JEDEC_WREN, NULL); nicintel_ee_bitset(eebar, EEC, EE_CS, 1); - internal_delay(1); + default_delay(1); /* data */ nicintel_ee_bitset(eebar, EEC, EE_CS, 0); @@ -394,7 +394,7 @@ static int nicintel_ee_write_82580(struct flashctx *flash, const uint8_t *buf, u break; } nicintel_ee_bitset(eebar, EEC, EE_CS, 1); - internal_delay(1); + default_delay(1); if (nicintel_ee_ready(eebar)) goto out; } |