par_masters: Reshuffle to remove forward declarations

Dispense with all these forward declarations by way of
ordering. Just deal with all the par_masters in one go
to be over and done with.

BUG=none
BRANCH=none
TEST=builds

Change-Id: I88e89992380195fee7c9de7ec57502ab980ec5df
Signed-off-by: Edward O'Callaghan <quasisec@google.com>
Reviewed-on: https://review.coreboot.org/c/flashrom/+/54873
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Anastasia Klimchuk <aklm@chromium.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>

1 files changed, 38 insertions, 40 deletions

diff --git a/nicrealtek.c b/nicrealtek.c
index 2208179c2..788c08841 100644
--- a/nicrealtek.c
+++ b/nicrealtek.c
@@ -35,8 +35,44 @@ const struct dev_entry nics_realtek[] = {
 	{0},
 };
 
-static void nicrealtek_chip_writeb(const struct flashctx *flash, uint8_t val, chipaddr addr);
-static uint8_t nicrealtek_chip_readb(const struct flashctx *flash, const chipaddr addr);
+static void nicrealtek_chip_writeb(const struct flashctx *flash, uint8_t val, chipaddr addr)
+{
+	/* Output addr and data, set WE to 0, set OE to 1, set CS to 0,
+	 * enable software access.
+	 */
+	OUTL(((uint32_t)addr & 0x01FFFF) | 0x0A0000 | (val << 24),
+	     io_base_addr + bios_rom_addr);
+	/* Output addr and data, set WE to 1, set OE to 1, set CS to 1,
+	 * enable software access.
+	 */
+	OUTL(((uint32_t)addr & 0x01FFFF) | 0x1E0000 | (val << 24),
+	     io_base_addr + bios_rom_addr);
+}
+
+static uint8_t nicrealtek_chip_readb(const struct flashctx *flash, const chipaddr addr)
+{
+	uint8_t val;
+
+	/* FIXME: Can we skip reading the old data and simply use 0? */
+	/* Read old data. */
+	val = INB(io_base_addr + bios_rom_data);
+	/* Output new addr and old data, set WE to 1, set OE to 0, set CS to 0,
+	 * enable software access.
+	 */
+	OUTL(((uint32_t)addr & 0x01FFFF) | 0x060000 | (val << 24),
+	     io_base_addr + bios_rom_addr);
+
+	/* Read new data. */
+	val = INB(io_base_addr + bios_rom_data);
+	/* Output addr and new data, set WE to 1, set OE to 1, set CS to 1,
+	 * enable software access.
+	 */
+	OUTL(((uint32_t)addr & 0x01FFFF) | 0x1E0000 | (val << 24),
+	     io_base_addr + bios_rom_addr);
+
+	return val;
+}
+
 static const struct par_master par_master_nicrealtek = {
 		.chip_readb		= nicrealtek_chip_readb,
 		.chip_readw		= fallback_chip_readw,
@@ -91,44 +127,6 @@ int nicrealtek_init(void)
 	return 0;
 }
 
-static void nicrealtek_chip_writeb(const struct flashctx *flash, uint8_t val, chipaddr addr)
-{
-	/* Output addr and data, set WE to 0, set OE to 1, set CS to 0,
-	 * enable software access.
-	 */
-	OUTL(((uint32_t)addr & 0x01FFFF) | 0x0A0000 | (val << 24),
-	     io_base_addr + bios_rom_addr);
-	/* Output addr and data, set WE to 1, set OE to 1, set CS to 1,
-	 * enable software access.
-	 */
-	OUTL(((uint32_t)addr & 0x01FFFF) | 0x1E0000 | (val << 24),
-	     io_base_addr + bios_rom_addr);
-}
-
-static uint8_t nicrealtek_chip_readb(const struct flashctx *flash, const chipaddr addr)
-{
-	uint8_t val;
-
-	/* FIXME: Can we skip reading the old data and simply use 0? */
-	/* Read old data. */
-	val = INB(io_base_addr + bios_rom_data);
-	/* Output new addr and old data, set WE to 1, set OE to 0, set CS to 0,
-	 * enable software access.
-	 */
-	OUTL(((uint32_t)addr & 0x01FFFF) | 0x060000 | (val << 24),
-	     io_base_addr + bios_rom_addr);
-
-	/* Read new data. */
-	val = INB(io_base_addr + bios_rom_data);
-	/* Output addr and new data, set WE to 1, set OE to 1, set CS to 1,
-	 * enable software access.
-	 */
-	OUTL(((uint32_t)addr & 0x01FFFF) | 0x1E0000 | (val << 24),
-	     io_base_addr + bios_rom_addr);
-
-	return val;
-}
-
 #else
 #error PCI port I/O access is not supported on this architecture yet.
 #endif