spi25_statusreg: delete spi_read_status_register()

Delete the spi_read_status_register() function because the generic
spi_read_register() function can be used instead.

This patch also converts all call sites over to spi_read_register().
A side effect is that error codes are now properly propagated and
checked.

BUG=b:195381327,b:153800563
BRANCH=none
TEST=flashrom -{r,w,E}
TEST=Tested with a W25Q128.W flash on a kasumi (AMD) dut.
     Read SR1/SR2 with --wp-status and activated various WP ranges
     that toggled bits in both SR1 and SR2.

Change-Id: I146b4b5439872e66c5d33e156451a729d248c7da
Signed-off-by: Nikolai Artemiev <nartemiev@google.com>
Reviewed-on: https://review.coreboot.org/c/flashrom/+/59529
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Edward O'Callaghan <quasisec@chromium.org>
Reviewed-by: Anastasia Klimchuk <aklm@chromium.org>

1 files changed, 7 insertions, 3 deletions

diff --git a/s25f.c b/s25f.c
index 0bd4a7cbe..82ca61069 100644
--- a/s25f.c
+++ b/s25f.c
@@ -133,9 +133,14 @@ static int s25fs_software_reset(struct flashctx *flash)
 
 static int s25f_poll_status(const struct flashctx *flash)
 {
-	uint8_t tmp = spi_read_status_register(flash);
+	while (true) {
+		uint8_t tmp;
+		if (spi_read_register(flash, STATUS1, &tmp))
+			return -1;
+
+		if ((tmp & SPI_SR_WIP) == 0)
+			break;
 
-	while (tmp & SPI_SR_WIP) {
 		/*
 		 * The WIP bit on S25F chips remains set to 1 if erase or
 		 * programming errors occur, so we must check for those
@@ -156,7 +161,6 @@ static int s25f_poll_status(const struct flashctx *flash)
 		}
 
 		programmer_delay(1000 * 10);
-		tmp = spi_read_status_register(flash);
 	}
 
 	return 0;