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| author | Nikolai Artemiev <nartemiev@google.com> | 2021-10-20 22:32:25 +1100 |
|---|---|---|
| committer | Anastasia Klimchuk <aklm@chromium.org> | 2022-02-28 07:58:43 +0000 |
| commit | b7ea3a9a5d481a09229abba0fe6d2509ef2713a1 (patch) | |
| tree | 01b5923330cf9ccd39da4c1802bda05d45e937da /spi.h | |
| parent | a0319804a03f69d6e21af2ce42e8fd311e2e6a8f (diff) | |
| download | flashrom-b7ea3a9a5d481a09229abba0fe6d2509ef2713a1.tar.gz flashrom-b7ea3a9a5d481a09229abba0fe6d2509ef2713a1.tar.bz2 flashrom-b7ea3a9a5d481a09229abba0fe6d2509ef2713a1.zip | |
spi25_statusreg,flashchips: add SR2 read/write support
This patch adds support for reading and writing the second status
register and enables it on a limited set of flash chips.
Chip support for RDSR2/WRSR2/extended WRSR is represented using feature
flags to be consistent with how other SPI capabilities are represented.
BUG=b:195381327,b:153800563
BRANCH=none
TEST=flashrom -{r,w,E}
TEST=flashrom --wp-{enable,disable,range,list,status} at end of patch series
TEST=logged SR2 read/write values during wp commands
Change-Id: I34a503b0958e8f2f22a2a993a6ea529eb46b41db
Signed-off-by: Nikolai Artemiev <nartemiev@google.com>
Reviewed-on: https://review.coreboot.org/c/flashrom/+/58570
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Anastasia Klimchuk <aklm@chromium.org>
Reviewed-by: Nico Huber <nico.h@gmx.de>
Diffstat (limited to 'spi.h')
| -rw-r--r-- | spi.h | 11 |
1 files changed, 11 insertions, 0 deletions
@@ -131,6 +131,11 @@ #define JEDEC_RDSR_OUTSIZE 0x01 #define JEDEC_RDSR_INSIZE 0x01 +/* Read Status Register 2 */ +#define JEDEC_RDSR2 0x35 +#define JEDEC_RDSR2_OUTSIZE 0x01 +#define JEDEC_RDSR2_INSIZE 0x01 + /* Status Register Bits */ #define SPI_SR_WIP (0x01 << 0) #define SPI_SR_WEL (0x01 << 1) @@ -146,6 +151,12 @@ #define JEDEC_WRSR 0x01 #define JEDEC_WRSR_OUTSIZE 0x02 #define JEDEC_WRSR_INSIZE 0x00 +#define JEDEC_WRSR_EXT_OUTSIZE 0x03 + +/* Write Status Register 2 */ +#define JEDEC_WRSR2 0x31 +#define JEDEC_WRSR2_OUTSIZE 0x02 +#define JEDEC_WRSR2_INSIZE 0x00 /* Enter 4-byte Address Mode */ #define JEDEC_ENTER_4_BYTE_ADDR_MODE 0xB7 |