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authorCarl-Daniel Hailfinger <c-d.hailfinger.devel.2006@gmx.net>2010-05-28 17:07:57 +0000
committerCarl-Daniel Hailfinger <c-d.hailfinger.devel.2006@gmx.net>2010-05-28 17:07:57 +0000
commitdc1cda15d48cdbc7d53e4cf86cf39844e4af2a8b (patch)
treef7d7123a8b474227d45bd9f0eae5b819d499b3a8 /spi.h
parent80f3d05e7356ec85f9ea27ae2e11245e0b6bb3c6 (diff)
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Add support for two-byte RES probes
Some chips implement the RES (0xab) opcode, but they use a non-standard two byte response instead of the usual one byte response. A two-byte response has the accuracy of REMS and RDID, so don't check for REMS/RDID availability before running a two-byte RES. Corresponding to flashrom svn r1017. Signed-off-by: Carl-Daniel Hailfinger <c-d.hailfinger.devel.2006@gmx.net> Acked-by: Stefan Reinauer <stepan@coresystems.de>
Diffstat (limited to 'spi.h')
-rw-r--r--spi.h2
1 files changed, 2 insertions, 0 deletions
diff --git a/spi.h b/spi.h
index 1b49d59ec..5cdf32b03 100644
--- a/spi.h
+++ b/spi.h
@@ -27,6 +27,7 @@
/* Read Electronic ID */
#define JEDEC_RDID 0x9f
#define JEDEC_RDID_OUTSIZE 0x01
+/* INSIZE may be 0x04 for some chips*/
#define JEDEC_RDID_INSIZE 0x03
/* AT25F512A has bit 3 as don't care bit in commands */
@@ -42,6 +43,7 @@
/* Read Electronic Signature */
#define JEDEC_RES 0xab
#define JEDEC_RES_OUTSIZE 0x04
+/* INSIZE may be 0x02 for some chips*/
#define JEDEC_RES_INSIZE 0x01
/* Write Enable */