summaryrefslogtreecommitdiffstats
path: root/spi25.c
diff options
context:
space:
mode:
authorFelix Singer <felixsinger@posteo.net>2022-08-19 02:57:40 +0200
committerAnastasia Klimchuk <aklm@chromium.org>2022-09-08 02:12:27 +0000
commit10f2dda8ddb69c421ce4e958e54cbd1ab63d5051 (patch)
treed6620a231e3e603d4b8a336b7826aa340b7d233d /spi25.c
parent05ac08f786cfd3f3f5b00b5dfb0849056d99245a (diff)
downloadflashrom-10f2dda8ddb69c421ce4e958e54cbd1ab63d5051.tar.gz
flashrom-10f2dda8ddb69c421ce4e958e54cbd1ab63d5051.tar.bz2
flashrom-10f2dda8ddb69c421ce4e958e54cbd1ab63d5051.zip
spi25.c: Retype appropriate variables with bool
Use the bool type instead of an integer for appropriate variables, since this represents their purpose much better. Signed-off-by: Felix Singer <felixsinger@posteo.net> Change-Id: Icd7e6478848c6f72817da16a5350d450bcc0bb5d Reviewed-on: https://review.coreboot.org/c/flashrom/+/66890 Reviewed-by: Anastasia Klimchuk <aklm@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Diffstat (limited to 'spi25.c')
-rw-r--r--spi25.c10
1 files changed, 5 insertions, 5 deletions
diff --git a/spi25.c b/spi25.c
index 445410630..6d160ebbb 100644
--- a/spi25.c
+++ b/spi25.c
@@ -37,7 +37,7 @@ enum id_type {
};
static struct {
- int is_cached;
+ bool is_cached;
unsigned char bytes[4]; /* enough to hold largest ID type */
} id_cache[NUM_ID_TYPES];
@@ -167,7 +167,7 @@ static int probe_spi_rdid_generic(struct flashctx *flash, int bytes)
msg_cinfo("%d byte RDID not supported on this SPI controller\n", bytes);
if (ret)
return 0;
- id_cache[idty].is_cached = 1;
+ id_cache[idty].is_cached = true;
}
rdid_get_ids(id_cache[idty].bytes, bytes, &id1, &id2);
@@ -191,7 +191,7 @@ int probe_spi_rems(struct flashctx *flash)
if (!id_cache[REMS].is_cached) {
if (spi_rems(flash, id_cache[REMS].bytes))
return 0;
- id_cache[REMS].is_cached = 1;
+ id_cache[REMS].is_cached = true;
}
id1 = id_cache[REMS].bytes[0];
@@ -247,7 +247,7 @@ int probe_spi_res2(struct flashctx *flash)
if (!id_cache[RES2].is_cached) {
if (spi_res(flash, id_cache[RES2].bytes, 2))
return 0;
- id_cache[RES2].is_cached = 1;
+ id_cache[RES2].is_cached = true;
}
id1 = id_cache[RES2].bytes[0];
@@ -267,7 +267,7 @@ int probe_spi_res3(struct flashctx *flash)
if (!id_cache[RES3].is_cached) {
if (spi_res(flash, id_cache[RES3].bytes, 3))
return 0;
- id_cache[RES3].is_cached = 1;
+ id_cache[RES3].is_cached = true;
}
id1 = (id_cache[RES3].bytes[0] << 8) | id_cache[RES3].bytes[1];