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| author | Nico Huber <nico.h@gmx.de> | 2018-03-13 18:01:05 +0100 |
|---|---|---|
| committer | Nico Huber <nico.h@gmx.de> | 2018-10-03 13:10:17 +0000 |
| commit | 57dbd64b33143964bb8eb91d33d72a2147f0091c (patch) | |
| tree | 1606d103406bf36144602971ca2ac970d3a61482 /spi25.c | |
| parent | 3eb5a8c82c00769bffc95c2c6c479de6d20dbd09 (diff) | |
| download | flashrom-57dbd64b33143964bb8eb91d33d72a2147f0091c.tar.gz flashrom-57dbd64b33143964bb8eb91d33d72a2147f0091c.tar.bz2 flashrom-57dbd64b33143964bb8eb91d33d72a2147f0091c.zip | |
flashchips: Add Spansion 25FL256S......0
The Spansion 25SFL256S supports 4BA through an extended address register,
a 4BA mode set by bit 7 of that register, or native 4BA instructions.
Enable the former only for now.
Unfortunately the S25SF256S uses another instruction to write the exten-
ded address register. So we add an override for the instruction byte.
Change-Id: I0a95a81dfe86434f049215ebd8477392391b9efc
Signed-off-by: Nico Huber <nico.h@gmx.de>
Tested-by: Michael Fuckner <michael@fuckner.net>
Reviewed-on: https://review.coreboot.org/25132
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: David Hendricks <david.hendricks@gmail.com>
Diffstat (limited to 'spi25.c')
| -rw-r--r-- | spi25.c | 3 |
1 files changed, 2 insertions, 1 deletions
@@ -341,13 +341,14 @@ static int spi_simple_write_cmd(struct flashctx *const flash, const uint8_t op, static int spi_write_extended_address_register(struct flashctx *const flash, const uint8_t regdata) { + const uint8_t op = flash->chip->wrea_override ? : JEDEC_WRITE_EXT_ADDR_REG; struct spi_command cmds[] = { { .writecnt = 1, .writearr = (const unsigned char[]){ JEDEC_WREN }, }, { .writecnt = 2, - .writearr = (const unsigned char[]){ JEDEC_WRITE_EXT_ADDR_REG, regdata }, + .writearr = (const unsigned char[]){ op, regdata }, }, NULL_SPI_CMD, }; |